mmu_cache_base Member List

This is the complete list of members for mmu_cache_base, including all inherited members.

ahb	AHBMaster<>
ahb_response_event	mmu_cache_base	protected
ahbaccess(tlm::tlm_generic_payload *trans)	AHBMaster<>	virtual
ahbaccess_dbg(tlm::tlm_generic_payload *trans)	AHBMaster<>	virtual
AHBDevice(ModuleName mn, uint32_t hindex, uint8_t vendorid, uint16_t deviceid, uint8_t version, uint8_t irq, BAR bar0, BAR bar1=BAR(), BAR bar2=BAR(), BAR bar3=BAR())	AHBDevice< BaseModule< DefaultBase > >
AHBDevice(ModuleName mn)	AHBDevice< BaseModule< DefaultBase > >
AHBMaster(ModuleName nm, uint8_t hindex, uint8_t vendor, uint8_t device, uint8_t version, uint8_t irq, AbstractionLayer ambaLayer, BAR bar0=BAR(), BAR bar1=BAR(), BAR bar2=BAR(), BAR bar3=BAR())	AHBMaster<>
ahbread(uint32_t addr, unsigned char *data, uint32_t length)	AHBMaster<>	virtual
ahbread(uint32_t addr, unsigned char *data, uint32_t length, sc_core::sc_time &delay, bool &cacheable, tlm::tlm_response_status &response)	AHBMaster<>	virtual
ahbread(uint32_t addr, unsigned char *data, uint32_t length, sc_core::sc_time &delay, bool &cacheable, bool is_lock, tlm::tlm_response_status &response)	AHBMaster<>	virtual
ahbread_dbg(uint32_t addr, unsigned char *data, uint32_t length)	AHBMaster<>	virtual
ahbwrite(uint32_t addr, unsigned char *data, uint32_t length)	AHBMaster<>	virtual
ahbwrite(uint32_t addr, unsigned char *data, uint32_t length, sc_core::sc_time &delay, tlm::tlm_response_status &response)	AHBMaster<>	virtual
ahbwrite(uint32_t addr, unsigned char *data, uint32_t length, sc_core::sc_time &delay, bool is_lock, tlm::tlm_response_status &response)	AHBMaster<>	virtual
ahbwrite_dbg(uint32_t addr, unsigned char *data, uint32_t length)	AHBMaster<>	virtual
BaseModule(ModuleName mn)	BaseModule< DefaultBase >	inline
bus_in_fifo	mmu_cache_base	protected
bus_read_completed	mmu_cache_base	protected
CACHE_CONTROL_REG	mmu_cache_base	protected
clk	CLKDevice
clkcng()	mmu_cache_base	virtual
CLKDevice()	CLKDevice
clock_cycle	CLKDevice	protected
DataThread()	AHBMaster<>
dcache	mmu_cache_base
dlocalram	mmu_cache_base
dorst()	mmu_cache_base	virtual
dyn_read_energy	mmu_cache_base	protected
dyn_read_energy_norm	mmu_cache_base	protected
dyn_reads	mmu_cache_base	protected
dyn_write_energy	mmu_cache_base	protected
dyn_write_energy_norm	mmu_cache_base	protected
dyn_writes	mmu_cache_base	protected
end_of_simulation()	mmu_cache_base
exec_data(const tlm::tlm_command cmd, const unsigned int &addr, unsigned char *ptr, unsigned int len, unsigned int asi, unsigned int *debug, unsigned int flush, unsigned int lock, sc_core::sc_time &delay, bool is_dbg, tlm::tlm_response_status &response)	mmu_cache_base	virtual
exec_instr(const unsigned int &addr, unsigned char *ptr, unsigned int asi, unsigned int *debug, const unsigned int &flush, sc_core::sc_time &delay, bool is_dbg)	mmu_cache_base	virtual
g_bar0	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar0haddr	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar0hcacheable	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar0hmask	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar0hprefetchable	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar0htype	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar1	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar1haddr	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar1hcacheable	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar1hmask	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar1hprefetchable	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar1htype	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar2	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar2haddr	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar2hcacheable	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar2hmask	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar2hprefetchable	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar2htype	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar3	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar3haddr	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar3hcacheable	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar3hmask	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar3hprefetchable	AHBDevice< BaseModule< DefaultBase > >	protected
g_bar3htype	AHBDevice< BaseModule< DefaultBase > >	protected
g_bars	AHBDevice< BaseModule< DefaultBase > >	protected
g_hdeviceid	AHBDevice< BaseModule< DefaultBase > >	protected
g_hindex	AHBDevice< BaseModule< DefaultBase > >	protected
g_hirq	AHBDevice< BaseModule< DefaultBase > >	protected
g_hvendorid	AHBDevice< BaseModule< DefaultBase > >	protected
g_hversion	AHBDevice< BaseModule< DefaultBase > >	protected
GC_HAS_CALLBACKS()	mmu_cache_base
get_ahb_bar_addr(uint32_t bar) const	AHBDevice< BaseModule< DefaultBase > >	virtual
get_ahb_bar_base(uint32_t bar) const	AHBDevice< BaseModule< DefaultBase > >	virtual
get_ahb_bar_cachable(uint32_t bar) const	AHBDevice< BaseModule< DefaultBase > >	inline
get_ahb_bar_mask(uint32_t bar) const	AHBDevice< BaseModule< DefaultBase > >	virtual
get_ahb_bar_prefetchable(uint32_t bar) const	AHBDevice< BaseModule< DefaultBase > >	inline
get_ahb_bar_relative_addr(uint32_t bar, uint32_t addr) const	AHBDevice< BaseModule< DefaultBase > >	virtual
get_ahb_bar_size(uint32_t bar) const	AHBDevice< BaseModule< DefaultBase > >	virtual
get_ahb_bar_type(uint32_t bar) const	AHBDevice< BaseModule< DefaultBase > >	virtual
get_ahb_base_addr()	AHBDevice< BaseModule< DefaultBase > >	virtual
get_ahb_base_addr_() const	AHBDevice< BaseModule< DefaultBase > >	virtual
get_ahb_device_id() const	AHBDevice< BaseModule< DefaultBase > >	virtual
get_ahb_device_info()	AHBDevice< BaseModule< DefaultBase > >	virtual
get_ahb_hindex() const	AHBDevice< BaseModule< DefaultBase > >	virtual
get_ahb_size()	AHBDevice< BaseModule< DefaultBase > >	virtual
get_ahb_size_() const	AHBDevice< BaseModule< DefaultBase > >	virtual
get_ahb_vendor_id() const	AHBDevice< BaseModule< DefaultBase > >	virtual
get_clock()	mmu_cache_base	virtual
globl_count	mmu_cache_base	protected
icache	mmu_cache_base
ilocalram	mmu_cache_base
init(uint32_t hindex, uint8_t vendorid, uint16_t deviceid, uint8_t version, uint8_t irq, BAR bar0, BAR bar1=BAR(), BAR bar2=BAR(), BAR bar3=BAR())	AHBDevice< BaseModule< DefaultBase > >
init_ahb_generics()	AHBDevice< BaseModule< DefaultBase > >
init_counters()	BaseModule< DefaultBase >	inlinevirtual
init_generics()	BaseModule< DefaultBase >	inlinevirtual
init_power()	BaseModule< DefaultBase >	inlinevirtual
init_registers()	BaseModule< DefaultBase >	inlinevirtual
int_power	mmu_cache_base	protected
int_power_cb(gs::gs_param_base &changed_param, gs::cnf::callback_type reason)	mmu_cache_base
int_power_norm	mmu_cache_base	protected
irq	mmu_cache_base
m_abstractionLayer	mmu_cache_base	protected
m_ambaLayer	AHBMaster<>	protected
m_api	BaseModule< DefaultBase >	protected
m_cached	mmu_cache_base	protected
m_counters	BaseModule< DefaultBase >	protected
m_dcen	mmu_cache_base	protected
m_dlram	mmu_cache_base	protected
m_dlramstart	mmu_cache_base	protected
m_dsnoop	mmu_cache_base	protected
m_EndRequestEvent	AHBMaster<>	protected
m_generics	BaseModule< DefaultBase >	protected
m_icen	mmu_cache_base	protected
m_ilram	mmu_cache_base	protected
m_ilramstart	mmu_cache_base	protected
m_master_id	mmu_cache_base	protected
m_mmu	mmu_cache_base
m_mmu_en	mmu_cache_base	protected
m_pow_mon	mmu_cache_base	protected
m_power	BaseModule< DefaultBase >	protected
m_reads	AHBMaster<>	protected
m_register	AHBDevice< BaseModule< DefaultBase > >	protected
m_ResponsePEQ	AHBMaster<>	protected
m_right_transactions	mmu_cache_base	protected
m_total_transactions	mmu_cache_base	protected
m_writes	AHBMaster<>	protected
mem_access()	mmu_cache_base	protected
mem_read(unsigned int addr, unsigned int asi, unsigned char *data, unsigned int length, sc_core::sc_time *t, unsigned int *debug, bool is_dbg, bool &cacheable, bool is_lock)	mmu_cache_base	virtual
mem_write(unsigned int addr, unsigned int asi, unsigned char *data, unsigned int length, sc_core::sc_time *t, unsigned int *debug, bool is_dbg, bool &cacheable, bool is_lock)	mmu_cache_base	virtual
mmu_cache_base(ModuleName name="", bool icen=true, uint32_t irepl=1, uint32_t isets=4, uint32_t ilinesize=8, uint32_t isetsize=8, uint32_t isetlock=true, uint32_t dcen=true, uint32_t drepl=1, uint32_t dsets=2, uint32_t dlinesize=4, uint32_t dsetsize=8, bool dsetlock=true, bool dsnoop=true, bool ilram=false, uint32_t ilramsize=0x000, uint32_t ilramstart=0x000, uint32_t dlram=false, uint32_t dlramsize=0x000, uint32_t dlramstart=0x000, uint32_t cached=0, bool mmu_en=true, uint32_t itlb_num=8, uint32_t dtlb_num=8, uint32_t tlb_type=0, uint32_t tlb_rep=1, uint32_t mmupgsz=0, uint32_t hindex=0, bool pow_mon=false, AbstractionLayer ambaLayer=amba::amba_LT)	mmu_cache_base
nb_transport_bw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, sc_core::sc_time &delay)	AHBMaster<>	virtual
onclk(const sc_core::sc_time &value, const sc_core::sc_time &time)	CLKDevice	virtual
onrst(const bool &value, const sc_core::sc_time &time)	CLKDevice	virtual
power_frame_starting_time	mmu_cache_base	protected
power_model()	mmu_cache_base
print_ahb_device_info(char *name) const	AHBDevice< BaseModule< DefaultBase > >	virtual
print_transport_statistics(const char *name) const	AHBMaster<>	virtual
read_ccr(bool internal)	mmu_cache_base	virtual
response_callback(tlm::tlm_generic_payload *trans)	mmu_cache_base	virtual
response_error	AHBMaster<>	protected
ResponseThread()	AHBMaster<>
rst	CLKDevice
SC_HAS_PROCESS(mmu_cache_base)	mmu_cache_base
AHBMaster<>::SC_HAS_PROCESS(AHBMaster)	AHBMaster<>
set_clk(sc_core::sc_clock &clk)	CLKDevice
set_clk(sc_core::sc_time period)	CLKDevice
set_clk(double period, sc_core::sc_time_unit base)	CLKDevice
set_irq(uint32_t tt)	mmu_cache_base	virtual
snoop	mmu_cache_base
snoopingCallBack(const t_snoop &snoop, const sc_core::sc_time &delay)	mmu_cache_base
SR_HAS_SIGNALS(mmu_cache_base)	mmu_cache_base
CLKDevice::SR_HAS_SIGNALS(CLKDevice)	CLKDevice
sta_power	mmu_cache_base	protected
sta_power_cb(gs::gs_param_base &changed_param, gs::cnf::callback_type reason)	mmu_cache_base
sta_power_norm	mmu_cache_base	protected
start_of_simulation()	mmu_cache_base
swi_power	mmu_cache_base	protected
swi_power_cb(gs::gs_param_base &changed_param, gs::cnf::callback_type reason)	mmu_cache_base
transport_statistics(tlm::tlm_generic_payload &gp)	AHBMaster<>	virtual
trigger_exception(unsigned int exception)=0	mmu_cache_base	pure virtual
wb_pointer	mmu_cache_base	protected
write_buf	mmu_cache_base	protected
write_ccr(unsigned char *data, unsigned int len, sc_core::sc_time *delay, unsigned int *debug, bool is_dbg)	mmu_cache_base	virtual
~AHBDevice()	AHBDevice< BaseModule< DefaultBase > >	virtual
~AHBDeviceBase()	AHBDeviceBase	inlinevirtual
~AHBMaster()	AHBMaster<>
~BaseModule()	BaseModule< DefaultBase >	inlinevirtual
~CLKDevice()	CLKDevice	virtual
~mem_if()	mem_if	inlinevirtual
~mmu_cache_base()	mmu_cache_base
~mmu_cache_if()	mmu_cache_if	inlinevirtual