SoCRocket
Transaction-Level Modeling Framework for Space Applications
SoCRocket
Transaction-Level Modeling Framework for Space Applications
This is the complete list of members for Memory, including all inherited members.
| b_transport(tlm::tlm_generic_payload &gp, sc_time &delay) | Memory | |
| b_transport(tlm::tlm_generic_payload &trans, sc_time &delay) | Memory | inlinevirtual |
| BaseMemory() | BaseMemory | |
| BaseModule(ModuleName mn) | BaseModule< DefaultBase > | inline |
| before_end_of_elaboration() | Memory | |
| bus | Memory | |
| clk | CLKDevice | |
| clkcng() | CLKDevice | inlinevirtual |
| CLKDevice() | CLKDevice | |
| clock_cycle | CLKDevice | protected |
| device_type enum name | MEMDevice | |
| dorst() | CLKDevice | virtual |
| dyn_read_energy | MemoryPower | |
| dyn_read_energy_norm | MemoryPower | |
| dyn_reads | MemoryPower | |
| dyn_reads_cb(gs::gs_param_base &changed_param, gs::cnf::callback_type reason) | MemoryPower | |
| dyn_reads_write_cb(gs::gs_param_base &changed_param, gs::cnf::callback_type reason) | MemoryPower | |
| dyn_write_energy | MemoryPower | |
| dyn_write_energy_norm | MemoryPower | |
| dyn_writes | MemoryPower | |
| dyn_writes_cb(gs::gs_param_base &changed_param, gs::cnf::callback_type reason) | MemoryPower | |
| dyn_writes_write_cb(gs::gs_param_base &changed_param, gs::cnf::callback_type reason) | MemoryPower | |
| end_of_simulation() | Memory | |
| erase(const uint32_t &start, const uint32_t &end) | BaseMemory | |
| erase_dbg(const uint32_t &start, const uint32_t &end) | BaseMemory | |
| g_elf_file | Memory | |
| g_storage_type | Memory | |
| GC_HAS_CALLBACKS() | Memory | |
| get_banks() const | MEMDevice | virtual |
| get_bits() const | MEMDevice | virtual |
| get_bsize() const | MEMDevice | virtual |
| get_cols() const | MEMDevice | virtual |
| get_device_info() const | MEMDevice | virtual |
| get_direct_mem_ptr(tlm::tlm_generic_payload &trans, tlm::tlm_dmi &dmi_data) | Memory | |
| get_size() const | MEMDevice | virtual |
| get_type() const | MEMDevice | virtual |
| get_type_name() const | MEMDevice | virtual |
| init_counters() | BaseModule< DefaultBase > | inlinevirtual |
| init_generics() | BaseModule< DefaultBase > | inlinevirtual |
| init_mem_generics() | MEMDevice | virtual |
| init_power() | BaseModule< DefaultBase > | inlinevirtual |
| init_registers() | BaseModule< DefaultBase > | inlinevirtual |
| int_power | MemoryPower | |
| int_power_norm | MemoryPower | |
| IO enum value | MEMDevice | |
| m_api | MemoryPower | |
| m_counters | BaseModule< DefaultBase > | protected |
| m_generics | BaseModule< DefaultBase > | protected |
| m_performance_counters | MemoryPower | |
| m_pow_mon | MemoryPower | |
| m_power | BaseModule< DefaultBase > | protected |
| m_reads | Memory | |
| m_reads_cb(gs::gs_param_base &changed_param, gs::cnf::callback_type reason) | Memory | |
| m_storage | BaseMemory | protected |
| m_writes | Memory | |
| m_writes_cb(gs::gs_param_base &changed_param, gs::cnf::callback_type reason) | Memory | |
| mem | Memory | |
| MEMDevice(sc_module_name name, device_type type, uint32_t banks=0, uint32_t bsize=0, uint32_t bits=32, uint32_t cols=0) | MEMDevice | |
| Memory(sc_module_name name, MEMDevice::device_type type=MEMDevice::SDRAM, uint32_t banks=2, uint32_t bsize=128 *1024 *1024, uint32_t bits=32, uint32_t cols=16, std::string implementation="ArrayStorage", bool pow_mon=false) | Memory | |
| Memory(sc_core::sc_module_name mn) | Memory | inline |
| MemoryPower(sc_module_name name, MEMDevice::device_type type=MEMDevice::SRAM, uint32_t banks=4, uint32_t bsize=128, uint32_t bits=32, uint32_t cols=16, bool pow_mon=false) | MemoryPower | |
| onclk(const sc_core::sc_time &value, const sc_core::sc_time &time) | CLKDevice | virtual |
| onrst(const bool &value, const sc_core::sc_time &time) | CLKDevice | virtual |
| power | MemoryPower | |
| power_frame_starting_time | MemoryPower | |
| power_model() | MemoryPower | |
| read(const uint32_t &addr) | BaseMemory | |
| read_block(const uint32_t &addr, uint8_t *data, const uint32_t &len) | BaseMemory | |
| read_block_dbg(const uint32_t &addr, uint8_t *data, const uint32_t &len) const | BaseMemory | |
| read_dbg(const uint32_t &addr) | BaseMemory | |
| reads | BaseMemory | |
| reads32 | BaseMemory | |
| ROM enum value | MEMDevice | |
| rst | CLKDevice | |
| SC_HAS_PROCESS(Memory) | Memory | |
| scireg_add_callback(scireg_callback &cb) | scireg_ns::scireg_region_if | inlinevirtual |
| scireg_get_bit_attributes(vector_byte &v, scireg_bit_attributes_type t, sc_dt::uint64 size, sc_dt::uint64 offset=0) const | scireg_ns::scireg_region_if | inlinevirtual |
| scireg_get_bit_width() const | BaseMemory | inlinevirtual |
| scireg_get_byte_width() const | scireg_ns::scireg_region_if | inlinevirtual |
| scireg_get_child_regions(std::vector< scireg_mapped_region > &mapped_regions, sc_dt::uint64 size=sc_dt::uint64(-1), sc_dt::uint64 offset=0) const | scireg_ns::scireg_region_if | inlinevirtual |
| scireg_get_dmi_granted(bool &granted, sc_dt::uint64 size, sc_dt::uint64 offset=0) const | BaseMemory | inlinevirtual |
| scireg_get_high_pos() const | BaseMemory | inlinevirtual |
| scireg_get_low_pos() const | BaseMemory | inlinevirtual |
| scireg_get_parent_modules(std::vector< sc_core::sc_module * > &v) const | scireg_ns::scireg_region_if | inlinevirtual |
| scireg_get_parent_regions(std::vector< scireg_region_if * > &v) const | scireg_ns::scireg_region_if | inlinevirtual |
| scireg_get_region_type(scireg_ns::scireg_region_type &t) const | BaseMemory | inlinevirtual |
| scireg_get_string_attribute(const char *&s, scireg_string_attribute_type t) const | scireg_ns::scireg_region_if | inlinevirtual |
| scireg_get_target_sockets(std::vector< sc_core::sc_object * > &v) const | scireg_ns::scireg_region_if | inlinevirtual |
| scireg_get_value_info(std::vector< scireg_value_info > &v) const | scireg_ns::scireg_region_if | inlinevirtual |
| scireg_read(scireg_ns::vector_byte &v, sc_dt::uint64 size, sc_dt::uint64 offset=0) const | BaseMemory | inlinevirtual |
| scireg_region_if() | scireg_ns::scireg_region_if | inline |
| scireg_remove_callback(scireg_callback &cb) | scireg_ns::scireg_region_if | inlinevirtual |
| scireg_write(const scireg_ns::vector_byte &v, sc_dt::uint64 size, sc_dt::uint64 offset=0) | BaseMemory | inlinevirtual |
| SDRAM enum value | MEMDevice | |
| set_clk(sc_core::sc_clock &clk) | CLKDevice | |
| set_clk(sc_core::sc_time period) | CLKDevice | |
| set_clk(double period, sc_core::sc_time_unit base) | CLKDevice | |
| set_storage(std::string implementation, uint32_t size) | BaseMemory | |
| SIZE enum value | Memory | |
| socket | Memory | |
| SR_HAS_SIGNALS(CLKDevice) | CLKDevice | |
| SRAM enum value | MEMDevice | |
| sta_power | MemoryPower | |
| sta_power_norm | MemoryPower | |
| start_of_simulation() | Memory | |
| swi_power | MemoryPower | |
| swi_power_cb(gs::gs_param_base &changed_param, gs::cnf::callback_type reason) | MemoryPower | |
| transport_dbg(tlm::tlm_generic_payload &gp) | Memory | |
| type typedef | MEMDevice | |
| write(const uint32_t &addr, const uint8_t &byte) | BaseMemory | |
| write_block(const uint32_t &addr, uint8_t *data, const uint32_t &len) | BaseMemory | |
| write_block_dbg(const uint32_t &addr, const uint8_t *data, const uint32_t &len) | BaseMemory | |
| write_dbg(const uint32_t &addr, const uint8_t &byte) | BaseMemory | |
| writes | BaseMemory | |
| writes32 | BaseMemory | |
| ~BaseMemory() | BaseMemory | |
| ~BaseModule() | BaseModule< DefaultBase > | inlinevirtual |
| ~CLKDevice() | CLKDevice | virtual |
| ~MEMDevice() | MEMDevice | virtual |
| ~Memory() | Memory | |
| ~MemoryPower() | MemoryPower | |
| ~scireg_region_if() | scireg_ns::scireg_region_if | inlinevirtual |