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MCtrl

Files

file  mctrl.cpp
 
file  mctrl.h
 

Classes

class  Mctrl
 This class is an TLM 2.0 Model of the Aeroflex Gaisler GRLIB mctrl. Further informations to the original VHDL Modle are available in the GRLIB IP Core User's Manual Section 66. More...
 

Functions

 SR_HAS_MODULE (Mctrl)
 
 Mctrl::SC_HAS_PROCESS (Mctrl)
 
 Mctrl::SR_HAS_SIGNALS (Mctrl)
 
 Mctrl::Mctrl (sc_module_name name, int romasel=28, int sdrasel=29, int romaddr=0x0, int rommask=0xE00, int ioaddr=0x200, int iomask=0xE00, int ramaddr=0x400, int rammask=0xC00, int paddr=0x0, int pmask=0xFFF, int wprot=0, int srbanks=4, int ram8=0, int ram16=0, int sepbus=0, int sdbits=32, int mobile=0, int sden=0, unsigned int hindex=0, unsigned int pindex=0, bool powmon=false, AbstractionLayer ambaLayer=amba::amba_LT)
 
 Mctrl::~Mctrl ()
 Default destructor. More...
 
void Mctrl::init_generics ()
 Initialize generics. More...
 
void Mctrl::init_registers ()
 Initialize registers. More...
 
 Mctrl::GC_HAS_CALLBACKS ()
 proclamation of callbacks More...
 
void Mctrl::end_of_elaboration ()
 Execute the callback registering when systemc reaches the end of elaboration. More...
 
void Mctrl::start_of_simulation ()
 Gathers information about the connected memory types when SystemC reaches the start of simulation. More...
 
void Mctrl::power_model ()
 Calculate power/energy values from normalized input data. More...
 
gs::cnf::callback_return_type Mctrl::sta_power_cb (gs::gs_param_base &changed_param, gs::cnf::callback_type reason)
 Static power callback. More...
 
gs::cnf::callback_return_type Mctrl::int_power_cb (gs::gs_param_base &changed_param, gs::cnf::callback_type reason)
 Dynamic/Internal power callback. More...
 
gs::cnf::callback_return_type Mctrl::swi_power_cb (gs::gs_param_base &changed_param, gs::cnf::callback_type reason)
 Dynamic/Switching power callback. More...
 
void Mctrl::end_of_simulation ()
 
sc_core::sc_time Mctrl::get_clock ()
 Returns clock cycle time from child. More...
 
void Mctrl::dorst ()
 
void Mctrl::launch_sdram_command ()
 
void Mctrl::switch_power_mode ()
 
void Mctrl::mcfg1_write ()
 
void Mctrl::mcfg2_write ()
 
uint32_t Mctrl::exec_func (tlm::tlm_generic_payload &trans, sc_core::sc_time &delay, bool debug=false)
 Encapsulation function for functional part of the model. More...
 
uint32_t Mctrl::transport_dbg (tlm_generic_payload &gp)
 
bool Mctrl::get_direct_mem_ptr (tlm::tlm_generic_payload &trans, tlm::tlm_dmi &dmi_data)
 
void Mctrl::invalidate_direct_mem_ptr (unsigned int index, sc_dt::uint64 start_range, sc_dt::uint64 end_range)
 
 Mctrl::MEMPort::MEMPort (uint32_t id, MEMDevice *dev)
 
 Mctrl::MEMPort::MEMPort ()
 

Variables

gs::socket::initiator_multi_socket< 32 > Mctrl::mem
 
uint32_t Mctrl::MEMPort::id
 
MEMDevice * Mctrl::MEMPort::dev
 
uint32_t Mctrl::MEMPort::base_addr
 
uint32_t Mctrl::MEMPort::addr
 
uint32_t Mctrl::MEMPort::length
 
static const uint32_t Mctrl::MCFG1 = 0x00
 
static const uint32_t Mctrl::MCFG2 = 0x04
 
static const uint32_t Mctrl::MCFG3 = 0x08
 
static const uint32_t Mctrl::MCFG4 = 0x0C
 
static const uint32_t Mctrl::MCFG1_WRITE_MASK = 0x1FE808FF
 
static const uint32_t Mctrl::MCFG1_IOBUSW = 0x18000000
 
static const uint32_t Mctrl::MCFG1_IBRDY = 0x04000000
 
static const uint32_t Mctrl::MCFG1_BEXCN = 0x02000000
 
static const uint32_t Mctrl::MCFG1_IO_WAITSTATES = 0x01E00000
 
static const uint32_t Mctrl::MCFG1_IOEN = 0x00080000
 
static const uint32_t Mctrl::MCFG1_PWEN = 0x00000800
 
static const uint32_t Mctrl::MCFG1_PROM_WIDTH = 0x00000300
 
static const uint32_t Mctrl::MCFG1_IO_WIDTH = 0x18000000
 
static const uint32_t Mctrl::MCFG1_PROM_WRITE_WS = 0x000000F0
 
static const uint32_t Mctrl::MCFG1_PROM_READ_WS = 0x0000000F
 
static const uint32_t Mctrl::MCFG2_WRITE_MASK = 0xFFD07EFF
 
static const uint32_t Mctrl::MCFG2_SDRF = 0x80000000
 
static const uint32_t Mctrl::MCFG2_TRP = 0x40000000
 
static const uint32_t Mctrl::MCFG2_SDRAM_TRFC = 0x38000000
 
static const uint32_t Mctrl::MCFG2_TCAS = 0x04000000
 
static const uint32_t Mctrl::MCFG2_SDRAM_BANKSZ = 0x03800000
 
static const uint32_t Mctrl::MCFG2_SDRAM_COSZ = 0x00600000
 
static const uint32_t Mctrl::MCFG2_SDRAM_CMD = 0x00180000
 
static const uint32_t Mctrl::MCFG2_D64 = 0x00040000
 
static const uint32_t Mctrl::MCFG2_MS = 0x00010000
 
static const uint32_t Mctrl::MCFG2_SE = 0x00004000
 
static const uint32_t Mctrl::MCFG2_SI = 0x00002000
 
static const uint32_t Mctrl::MCFG2_RAM_BANK_SIZE = 0x00001E00
 
static const uint32_t Mctrl::MCFG2_RBRDY = 0x00000080
 
static const uint32_t Mctrl::MCFG2_RMW = 0x00000040
 
static const uint32_t Mctrl::MCFG2_RAM_WIDTH = 0x00000030
 
static const uint32_t Mctrl::MCFG2_RAM_WRITE_WS = 0x0000000C
 
static const uint32_t Mctrl::MCFG2_RAM_READ_WS = 0x00000003
 
static const uint32_t Mctrl::MCFG3_WRITE_MASK = 0x07FFF000
 
static const uint32_t Mctrl::MCFG3_SDRAM_RLD_VAL = 0x07FFF000
 
static const uint32_t Mctrl::MCFG4_WRITE_MASK = 0xE0F7007F
 
static const uint32_t Mctrl::MCFG4_ME = 0x80000000
 
static const uint32_t Mctrl::MCFG4_CE = 0x40000000
 
static const uint32_t Mctrl::MCFG4_EM = 0x20000000
 
static const uint32_t Mctrl::MCFG4_TXSR = 0x00F00000
 
static const uint32_t Mctrl::MCFG4_PMODE = 0x00070000
 
static const uint32_t Mctrl::MCFG4_DC = 0x00000060
 
static const uint32_t Mctrl::MCFG4_TCSR = 0x00000018
 
static const uint32_t Mctrl::MCFG4_PASR = 0x00000007
 
static const uint32_t Mctrl::MCFG1_IOBUSW_DEFAULT = 0x18000000
 
static const uint32_t Mctrl::MCFG1_IBRDY_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG1_BEXCN_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG1_IO_WAITSTATES_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG1_IOEN_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG1_PWEN_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG1_PROM_WIDTH_DEFAULT = 0x00000300
 
static const uint32_t Mctrl::MCFG1_PROM_WRITE_WS_DEFAULT = 0x000000F0
 
static const uint32_t Mctrl::MCFG1_PROM_READ_WS_DEFAULT = 0x0000000F
 
static const uint32_t Mctrl::MCFG1_DEFAULT = 0x180003FF
 
static const uint32_t Mctrl::MCFG2_SDRF_DEFAULT = 0x80000000
 
static const uint32_t Mctrl::MCFG2_TRP_DEFAULT = 0x40000000
 
static const uint32_t Mctrl::MCFG2_SDRAM_TRFC_DEFAULT = 0x38000000
 
static const uint32_t Mctrl::MCFG2_TCAS_DEFAULT = 0x04000000
 
static const uint32_t Mctrl::MCFG2_SDRAM_BANKSZ_DEFAULT = 0x03000000
 
static const uint32_t Mctrl::MCFG2_SDRAM_COSZ_DEFAULT = 0x00600000
 
static const uint32_t Mctrl::MCFG2_SDRAM_CMD_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG2_D64_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG2_MS_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG2_SE_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG2_SI_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG2_RAM_BANK_SIZE_DEFAULT = 0x00001C00
 
static const uint32_t Mctrl::MCFG2_RBRDY_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG2_RMW_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG2_RAM_WIDTH_DEFAULT = 0x00000030
 
static const uint32_t Mctrl::MCFG2_RAM_WRITE_WS_DEFAULT = 0x0000000C
 
static const uint32_t Mctrl::MCFG2_RAM_READ_WS_DEFAULT = 0x00000003
 
static const uint32_t Mctrl::MCFG2_DEFAULT = 0xFF601C3F
 
static const uint32_t Mctrl::MCFG3_DEFAULT = 0x07FFF000
 
static const uint32_t Mctrl::MCFG4_ME_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG4_CE_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG4_EM_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG4_TXSR_DEFAULT = 0x00F00000
 
static const uint32_t Mctrl::MCFG4_PMODE_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG4_DS_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG4_TCSR_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG4_PASR_DEFAULT = 0x00000000
 
static const uint32_t Mctrl::MCFG4_DEFAULT = 0x00F00000
 

Detailed Description

Function Documentation

void Mctrl::dorst ( )
virtual

Reset Handler

Executed on rst state change. Performs a full reset of the Model. So it will set all registers to defaults, etc.

Parameters
valueThe new Value of the Signal.
delayA possible delay. Which means the reset might be performed in the future (Not used for resets!).

Reimplemented from CLKDevice.

References Mctrl::MCFG1, Mctrl::MCFG2, Mctrl::MCFG2_MS, Mctrl::MCFG2_SDRF, Mctrl::MCFG2_SE, Mctrl::MCFG3, Mctrl::MCFG4, Mctrl::MCFG4_ME, APBSlave::r, and set.

Referenced by Mctrl::end_of_elaboration().

void Mctrl::end_of_elaboration ( )

Execute the callback registering when systemc reaches the end of elaboration.

References Mctrl::dorst().

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void Mctrl::end_of_simulation ( )

SystemC end of simulation handler. It's needed to print performance counter

References sr_param_t< T >::getValue(), setup::name, AHBSlave< APBSlave >::print_transport_statistics(), v::report, and Mctrl::switch_power_mode().

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uint32_t Mctrl::exec_func ( tlm::tlm_generic_payload &  trans,
sc_core::sc_time &  delay,
bool  debug = false 
)

Encapsulation function for functional part of the model.

References CLKDevice::clock_cycle, v::debug, v::error, MEMDevice::IO, Mctrl::MCFG1, Mctrl::MCFG1_IBRDY, Mctrl::MCFG2, Mctrl::MCFG2_RBRDY, Mctrl::mem, setup::name, APBSlave::r, pysc::api::cci::read(), MEMDevice::ROM, MEMDevice::SDRAM, MEMDevice::SRAM, v::uint32, and v::warn.

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Mctrl::GC_HAS_CALLBACKS ( )

proclamation of callbacks

sc_core::sc_time Mctrl::get_clock ( )
virtual

Returns clock cycle time from child.

Implements AHBSlave< APBSlave >.

References CLKDevice::clock_cycle.

bool Mctrl::get_direct_mem_ptr ( tlm::tlm_generic_payload &  trans,
tlm::tlm_dmi &  dmi_data 
)

References Mctrl::mem, result, and start.

Referenced by Mctrl::Mctrl().

void Mctrl::init_generics ( )
virtual

Initialize generics.

Reimplemented from BaseModule< DefaultBase >.

References sr_param_base::add_properties().

Referenced by Mctrl::Mctrl().

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void Mctrl::init_registers ( )
virtual

Initialize registers.

Reimplemented from BaseModule< DefaultBase >.

References sr_register< DATA_TYPE >::callback(), sr_register< DATA_TYPE >::create_field(), sr_register_bank< ADDR_TYPE, DATA_TYPE >::create_register(), Mctrl::launch_sdram_command(), Mctrl::MCFG1_DEFAULT, Mctrl::mcfg1_write(), Mctrl::MCFG1_WRITE_MASK, Mctrl::MCFG2_DEFAULT, Mctrl::mcfg2_write(), Mctrl::MCFG2_WRITE_MASK, Mctrl::MCFG3_DEFAULT, Mctrl::MCFG3_WRITE_MASK, Mctrl::MCFG4_DEFAULT, Mctrl::MCFG4_WRITE_MASK, APBSlave::r, SR_POST_WRITE, and Mctrl::switch_power_mode().

Referenced by Mctrl::Mctrl().

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gs::cnf::callback_return_type Mctrl::int_power_cb ( gs::gs_param_base &  changed_param,
gs::cnf::callback_type  reason 
)

Dynamic/Internal power callback.

References GC_RETURN_OK.

void Mctrl::invalidate_direct_mem_ptr ( unsigned int  index,
sc_dt::uint64  start_range,
sc_dt::uint64  end_range 
)

References AHBSlave< APBSlave >::ahb.

Referenced by Mctrl::Mctrl().

void Mctrl::launch_sdram_command ( )

Performing an SDRAM Command

This function is executed by the SDRAM Command Field in the MCFG2 Register. It will perform the coresponding state change to the SDRAM Controler and RAM. For more information read the corresponding Secton from the GRLIB IP Core User's Manual: Section 66.9.

References CLKDevice::clock_cycle, Mctrl::MCFG2, Mctrl::MCFG2_SDRAM_CMD, Mctrl::MCFG2_SDRAM_TRFC_DEFAULT, Mctrl::MCFG2_TRP_DEFAULT, APBSlave::r, and set.

Referenced by Mctrl::init_registers().

void Mctrl::mcfg1_write ( )

References v::debug, Mctrl::MCFG1, Mctrl::MCFG1_PROM_WIDTH, setup::name, APBSlave::r, v::uint32, and v::warn.

Referenced by Mctrl::init_registers().

void Mctrl::mcfg2_write ( )

References v::debug, Mctrl::MCFG2, Mctrl::MCFG2_RAM_WIDTH, Mctrl::MCFG2_SE, setup::name, APBSlave::r, v::uint32, and v::warn.

Referenced by Mctrl::init_registers().

Mctrl::Mctrl ( sc_module_name  name,
int  romasel = 28,
int  sdrasel = 29,
int  romaddr = 0x0,
int  rommask = 0xE00,
int  ioaddr = 0x200,
int  iomask = 0xE00,
int  ramaddr = 0x400,
int  rammask = 0xC00,
int  paddr = 0x0,
int  pmask = 0xFFF,
int  wprot = 0,
int  srbanks = 4,
int  ram8 = 0,
int  ram16 = 0,
int  sepbus = 0,
int  sdbits = 32,
int  mobile = 0,
int  sden = 0,
unsigned int  hindex = 0,
unsigned int  pindex = 0,
bool  powmon = false,
AbstractionLayer  ambaLayer = amba::amba_LT 
)

Creates a new Instance of an MCtrl.

Parameters
nameThe SystemC name of the component to be created.
romasel
sdrasel
romaddr
rommask
ioaddr
iomask
ramaddr
rammask
paddr
pmask
wprot
srbanks
ram8
ram16
sepbus
sdbits
mobile
sden
hindex
pindex
powermon
abstractionLayerAll constructor parameter are directly related to an VHDL Generic in the original Model. Therefore read the GRLIB IP Core User's Manual Section 66.15 for more information.

References AHBSlave< APBSlave >::ahb, APBSlave::apb, APBIO, v::error, APBSlaveSocket< BUSWIDTH, ADDR_TYPE, DATA_TYPE >::get_base_addr(), Mctrl::get_direct_mem_ptr(), APBSlaveSocket< BUSWIDTH, ADDR_TYPE, DATA_TYPE >::get_size(), APBDevice< BaseModule< DefaultBase > >::init_apb(), Mctrl::init_generics(), Mctrl::init_registers(), Mctrl::invalidate_direct_mem_ptr(), Mctrl::mem, setup::name, pindex, and srInfo.

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Mctrl::MEMPort::MEMPort ( uint32_t  id,
MEMDevice *  dev 
)
Mctrl::MEMPort::MEMPort ( )
void Mctrl::power_model ( )

Calculate power/energy values from normalized input data.

References CLKDevice::clock_cycle.

Referenced by Mctrl::start_of_simulation().

Mctrl::SC_HAS_PROCESS ( Mctrl  )
SR_HAS_MODULE ( Mctrl  )
Mctrl::SR_HAS_SIGNALS ( Mctrl  )
gs::cnf::callback_return_type Mctrl::sta_power_cb ( gs::gs_param_base &  changed_param,
gs::cnf::callback_type  reason 
)

Static power callback.

References GC_RETURN_OK.

void Mctrl::start_of_simulation ( )

Gathers information about the connected memory types when SystemC reaches the start of simulation.

References v::debug, device, v::error, AHBDevice< APBSlave >::get_ahb_bar_addr(), MEMDevice::get_bits(), MEMDevice::get_bsize(), MEMDevice::get_cols(), MEMDevice::get_type(), i, MEMDevice::IO, Mctrl::MCFG1, Mctrl::MCFG2, Mctrl::mem, setup::name, Mctrl::power_model(), APBSlave::r, MEMDevice::ROM, MEMDevice::SDRAM, MEMDevice::SRAM, and v::warn.

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gs::cnf::callback_return_type Mctrl::swi_power_cb ( gs::gs_param_base &  changed_param,
gs::cnf::callback_type  reason 
)

Dynamic/Switching power callback.

References GC_RETURN_OK.

void Mctrl::switch_power_mode ( )

Performing an Power-Mode change

This function is executed by the pmode Field in the MCFG4 Register. It will perform the coresponding state change to the Memory Controler and RAM. For more information read the corresponding Secton from the GRLIB IP Core User's Manual: Section 66.9.

References v::debug, sr_param_t< T >::getValue(), Mctrl::MCFG4, Mctrl::MCFG4_PASR, Mctrl::mem, setup::name, APBSlave::r, and start.

Referenced by Mctrl::end_of_simulation(), and Mctrl::init_registers().

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uint32_t Mctrl::transport_dbg ( tlm_generic_payload &  gp)

References v::error, Mctrl::mem, setup::name, result, and v::uint32.

Mctrl::~Mctrl ( )

Default destructor.

Variable Documentation

uint32_t Mctrl::MEMPort::addr
uint32_t Mctrl::MEMPort::base_addr
MEMDevice* Mctrl::MEMPort::dev
uint32_t Mctrl::MEMPort::id
uint32_t Mctrl::MEMPort::length
const uint32_t Mctrl::MCFG1 = 0x00
static

Referenced by Mctrl::dorst(), Mctrl::exec_func(), Mctrl::mcfg1_write(), and Mctrl::start_of_simulation().

const uint32_t Mctrl::MCFG1_BEXCN = 0x02000000
static
const uint32_t Mctrl::MCFG1_BEXCN_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG1_DEFAULT = 0x180003FF
static

Referenced by Mctrl::init_registers().

const uint32_t Mctrl::MCFG1_IBRDY = 0x04000000
static

Referenced by Mctrl::exec_func().

const uint32_t Mctrl::MCFG1_IBRDY_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG1_IO_WAITSTATES = 0x01E00000
static
const uint32_t Mctrl::MCFG1_IO_WAITSTATES_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG1_IO_WIDTH = 0x18000000
static
const uint32_t Mctrl::MCFG1_IOBUSW = 0x18000000
static
const uint32_t Mctrl::MCFG1_IOBUSW_DEFAULT = 0x18000000
static
const uint32_t Mctrl::MCFG1_IOEN = 0x00080000
static
const uint32_t Mctrl::MCFG1_IOEN_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG1_PROM_READ_WS = 0x0000000F
static
const uint32_t Mctrl::MCFG1_PROM_READ_WS_DEFAULT = 0x0000000F
static
const uint32_t Mctrl::MCFG1_PROM_WIDTH = 0x00000300
static

Referenced by Mctrl::mcfg1_write().

const uint32_t Mctrl::MCFG1_PROM_WIDTH_DEFAULT = 0x00000300
static
const uint32_t Mctrl::MCFG1_PROM_WRITE_WS = 0x000000F0
static
const uint32_t Mctrl::MCFG1_PROM_WRITE_WS_DEFAULT = 0x000000F0
static
const uint32_t Mctrl::MCFG1_PWEN = 0x00000800
static
const uint32_t Mctrl::MCFG1_PWEN_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG1_WRITE_MASK = 0x1FE808FF
static

Referenced by Mctrl::init_registers().

const uint32_t Mctrl::MCFG2 = 0x04
static

Referenced by Mctrl::dorst(), Mctrl::exec_func(), Mctrl::launch_sdram_command(), Mctrl::mcfg2_write(), and Mctrl::start_of_simulation().

const uint32_t Mctrl::MCFG2_D64 = 0x00040000
static
const uint32_t Mctrl::MCFG2_D64_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG2_DEFAULT = 0xFF601C3F
static

Referenced by Mctrl::init_registers().

const uint32_t Mctrl::MCFG2_MS = 0x00010000
static

Referenced by Mctrl::dorst().

const uint32_t Mctrl::MCFG2_MS_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG2_RAM_BANK_SIZE = 0x00001E00
static
const uint32_t Mctrl::MCFG2_RAM_BANK_SIZE_DEFAULT = 0x00001C00
static
const uint32_t Mctrl::MCFG2_RAM_READ_WS = 0x00000003
static
const uint32_t Mctrl::MCFG2_RAM_READ_WS_DEFAULT = 0x00000003
static
const uint32_t Mctrl::MCFG2_RAM_WIDTH = 0x00000030
static

Referenced by Mctrl::mcfg2_write().

const uint32_t Mctrl::MCFG2_RAM_WIDTH_DEFAULT = 0x00000030
static
const uint32_t Mctrl::MCFG2_RAM_WRITE_WS = 0x0000000C
static
const uint32_t Mctrl::MCFG2_RAM_WRITE_WS_DEFAULT = 0x0000000C
static
const uint32_t Mctrl::MCFG2_RBRDY = 0x00000080
static

Referenced by Mctrl::exec_func().

const uint32_t Mctrl::MCFG2_RBRDY_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG2_RMW = 0x00000040
static
const uint32_t Mctrl::MCFG2_RMW_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG2_SDRAM_BANKSZ = 0x03800000
static
const uint32_t Mctrl::MCFG2_SDRAM_BANKSZ_DEFAULT = 0x03000000
static
const uint32_t Mctrl::MCFG2_SDRAM_CMD = 0x00180000
static

Referenced by Mctrl::launch_sdram_command().

const uint32_t Mctrl::MCFG2_SDRAM_CMD_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG2_SDRAM_COSZ = 0x00600000
static
const uint32_t Mctrl::MCFG2_SDRAM_COSZ_DEFAULT = 0x00600000
static
const uint32_t Mctrl::MCFG2_SDRAM_TRFC = 0x38000000
static
const uint32_t Mctrl::MCFG2_SDRAM_TRFC_DEFAULT = 0x38000000
static

Referenced by Mctrl::launch_sdram_command().

const uint32_t Mctrl::MCFG2_SDRF = 0x80000000
static

Referenced by Mctrl::dorst().

const uint32_t Mctrl::MCFG2_SDRF_DEFAULT = 0x80000000
static
const uint32_t Mctrl::MCFG2_SE = 0x00004000
static

Referenced by Mctrl::dorst(), and Mctrl::mcfg2_write().

const uint32_t Mctrl::MCFG2_SE_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG2_SI = 0x00002000
static
const uint32_t Mctrl::MCFG2_SI_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG2_TCAS = 0x04000000
static
const uint32_t Mctrl::MCFG2_TCAS_DEFAULT = 0x04000000
static
const uint32_t Mctrl::MCFG2_TRP = 0x40000000
static
const uint32_t Mctrl::MCFG2_TRP_DEFAULT = 0x40000000
static

Referenced by Mctrl::launch_sdram_command().

const uint32_t Mctrl::MCFG2_WRITE_MASK = 0xFFD07EFF
static

Referenced by Mctrl::init_registers().

const uint32_t Mctrl::MCFG3 = 0x08
static

Referenced by Mctrl::dorst().

const uint32_t Mctrl::MCFG3_DEFAULT = 0x07FFF000
static

Referenced by Mctrl::init_registers().

const uint32_t Mctrl::MCFG3_SDRAM_RLD_VAL = 0x07FFF000
static
const uint32_t Mctrl::MCFG3_WRITE_MASK = 0x07FFF000
static

Referenced by Mctrl::init_registers().

const uint32_t Mctrl::MCFG4 = 0x0C
static

Referenced by Mctrl::dorst(), and Mctrl::switch_power_mode().

const uint32_t Mctrl::MCFG4_CE = 0x40000000
static
const uint32_t Mctrl::MCFG4_CE_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG4_DC = 0x00000060
static
const uint32_t Mctrl::MCFG4_DEFAULT = 0x00F00000
static

Referenced by Mctrl::init_registers().

const uint32_t Mctrl::MCFG4_DS_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG4_EM = 0x20000000
static
const uint32_t Mctrl::MCFG4_EM_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG4_ME = 0x80000000
static

Referenced by Mctrl::dorst().

const uint32_t Mctrl::MCFG4_ME_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG4_PASR = 0x00000007
static

Referenced by Mctrl::switch_power_mode().

const uint32_t Mctrl::MCFG4_PASR_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG4_PMODE = 0x00070000
static
const uint32_t Mctrl::MCFG4_PMODE_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG4_TCSR = 0x00000018
static
const uint32_t Mctrl::MCFG4_TCSR_DEFAULT = 0x00000000
static
const uint32_t Mctrl::MCFG4_TXSR = 0x00F00000
static
const uint32_t Mctrl::MCFG4_TXSR_DEFAULT = 0x00F00000
static
const uint32_t Mctrl::MCFG4_WRITE_MASK = 0xE0F7007F
static

Referenced by Mctrl::init_registers().

gs::socket::initiator_multi_socket<32> Mctrl::mem

Memory Master Socket

Initiate communication with memory modules.

Referenced by Mctrl::exec_func(), Mctrl::get_direct_mem_ptr(), Mctrl::Mctrl(), sc_main(), Mctrl::start_of_simulation(), Mctrl::switch_power_mode(), and Mctrl::transport_dbg().