SoCRocket
Transaction-Level Modeling Framework for Space Applications
Classes | |
| struct | satcan_regs |
| struct | irq_reg |
Macros | |
| #define | MOD 0 |
| #define | CMR 1 |
| #define | SR 2 |
| #define | IR 3 |
| #define | IER 4 |
| #define | RES 5 |
| #define | BTR0 6 |
| #define | BTR1 7 |
| #define | OCR 8 |
| #define | TST 9 |
| #define | RES2 10 |
| #define | ALC 11 |
| #define | ECC 12 |
| #define | EWL 13 |
| #define | RXERR 14 |
| #define | TXERR 15 |
| #define | FI 16 |
| #define | ID1 17 |
| #define | ID2 18 |
| #define | EFF_ID3 19 |
| #define | EFF_ID4 20 |
| #define | SFF_D1 19 |
| #define | SFF_D2 20 |
| #define | SFF_D3 21 |
| #define | SFF_D4 22 |
| #define | SFF_D5 23 |
| #define | SFF_D6 24 |
| #define | SFF_D7 25 |
| #define | SFF_D8 26 |
| #define | EFF_D1 21 |
| #define | EFF_D2 22 |
| #define | EFF_D3 23 |
| #define | EFF_D4 24 |
| #define | EFF_D5 25 |
| #define | EFF_D6 26 |
| #define | EFF_D7 27 |
| #define | EFF_D8 28 |
| #define | ACR0 16 |
| #define | ACR1 17 |
| #define | ACR2 18 |
| #define | ACR3 19 |
| #define | AMR0 20 |
| #define | AMR1 21 |
| #define | AMR2 22 |
| #define | AMR3 23 |
| #define | NMSG_FIFO 27 |
| #define | NMSG_FIFO2 28 |
| #define | RMC 29 |
| #define | RBSA 30 |
| #define | CDR 31 |
| #define | RXFIFO_START 32 |
| #define | TXBUF_START 96 |
| #define | MOD_RM 0x1 |
| #define | MOD_LOM 0x2 |
| #define | MOD_STM 0x4 |
| #define | MOD_AFM 0x8 |
| #define | CMR_TR 0x1 |
| #define | CMR_AT 0x2 |
| #define | CMR_RRB 0x4 |
| #define | CMR_CDO 0x8 |
| #define | CMR_SRR 0x10 |
| #define | SR_RBS 0x1 |
| #define | SR_DOS 0x2 |
| #define | SR_TBS 0x4 |
| #define | SR_TCS 0x8 |
| #define | SR_RS 0x10 |
| #define | SR_TS 0x20 |
| #define | SR_ES 0x40 |
| #define | SR_BS 0x80 |
| #define | DATA 16*1024 |
| #define | INT_EN 1 |
| #define | FIFO 3 |
| #define | CMD0 6 |
| #define | CMD1 7 |
| #define | START_CTC 8 |
| #define | STOP_CTC 10 |
| #define | RAM_BASE 9 |
| #define | DPS_ACT 10 |
| #define | PLL_RST 11 |
| #define | PLL_CMD 12 |
| #define | PLL_STAT 13 |
| #define | PLL_OFF 14 |
| #define | DMA 15 |
| #define | DMA_TX_1_CUR 16 |
| #define | DMA_TX_1_END 17 |
| #define | DMA_TX_2_CUR 18 |
| #define | DMA_TX_2_END 19 |
| #define | RX 20 |
| #define | FILTER_SETUP 21 |
| #define | FILTER_START 20 |
| #define | FILTER_STOP 21 |
Functions | |
| void | reset_mode (void) |
| void | operating_mode (void) |
| void | can_filter (int mode, unsigned char *acr, unsigned char *amr) |
| void | can_send_eff (int id, int rtr, int dlc, unsigned char *data) |
| int | can_tx_complete (void) |
| int | can_read_eff (int *id, int *rtr, unsigned char *data) |
| void | can_init (int fmode, unsigned char *acr, unsigned char *amr) |
| void * | catch_interrupt (void func(), int irq) |
| enable_irq (int irqn) | |
| disable_irq (int irqn) | |
| force_irq (int irqn) | |
| void | sc_irq_handler (int irqn) |
| void | oc_irq_handler (int irqn) |
| satcan_test (unsigned int sc_addr, int sc_irq, unsigned int oc_addr, int oc_irq, unsigned int mux_addr, unsigned int bus) | |
Variables | |
| volatile unsigned char * | oc_reg |
| struct satcan_regs * | r |
| struct irq_reg * | irq = (struct irq_reg *) 0x80000200 |
| volatile unsigned char * | mem |
| volatile int | oc_irq_done |
| volatile int | sc_irq_done |
| volatile unsigned int | irq_oc =0 |
| volatile unsigned int | irq_sc =0 |
| volatile unsigned int | s =0 |
| volatile unsigned int | d =0 |
| #define ACR0 16 |
Referenced by can_filter().
| #define ACR1 17 |
| #define ACR2 18 |
| #define ACR3 19 |
| #define ALC 11 |
| #define AMR0 20 |
Referenced by can_filter().
| #define AMR1 21 |
| #define AMR2 22 |
| #define AMR3 23 |
| #define BTR0 6 |
Referenced by can_init().
| #define BTR1 7 |
Referenced by can_init().
| #define CDR 31 |
Referenced by can_init(), and satcan_test().
| #define CMD0 6 |
Referenced by satcan_test().
| #define CMD1 7 |
Referenced by satcan_test().
| #define CMR 1 |
Referenced by can_read_eff(), and can_send_eff().
| #define CMR_AT 0x2 |
| #define CMR_CDO 0x8 |
| #define CMR_RRB 0x4 |
Referenced by can_read_eff().
| #define CMR_SRR 0x10 |
| #define CMR_TR 0x1 |
Referenced by can_send_eff().
| #define DATA 16*1024 |
Referenced by satcan_test().
| #define DMA 15 |
Referenced by satcan_test().
| #define DMA_TX_1_CUR 16 |
Referenced by satcan_test().
| #define DMA_TX_1_END 17 |
Referenced by satcan_test().
| #define DMA_TX_2_CUR 18 |
| #define DMA_TX_2_END 19 |
| #define DPS_ACT 10 |
| #define ECC 12 |
| #define EFF_D1 21 |
Referenced by can_read_eff(), and can_send_eff().
| #define EFF_D2 22 |
| #define EFF_D3 23 |
| #define EFF_D4 24 |
| #define EFF_D5 25 |
| #define EFF_D6 26 |
| #define EFF_D7 27 |
| #define EFF_D8 28 |
| #define EFF_ID3 19 |
Referenced by can_read_eff(), and can_send_eff().
| #define EFF_ID4 20 |
Referenced by can_read_eff(), and can_send_eff().
| #define EWL 13 |
| #define FI 16 |
Referenced by can_read_eff(), and can_send_eff().
| #define FIFO 3 |
Referenced by sc_irq_handler().
| #define FILTER_SETUP 21 |
| #define FILTER_START 20 |
| #define FILTER_STOP 21 |
| #define ID1 17 |
Referenced by can_read_eff(), and can_send_eff().
| #define ID2 18 |
Referenced by can_read_eff(), and can_send_eff().
| #define IER 4 |
Referenced by can_init().
| #define INT_EN 1 |
Referenced by satcan_test().
| #define IR 3 |
Referenced by oc_irq_handler().
| #define MOD 0 |
Referenced by can_filter(), can_init(), operating_mode(), and reset_mode().
| #define MOD_AFM 0x8 |
Referenced by can_filter().
| #define MOD_LOM 0x2 |
| #define MOD_RM 0x1 |
Referenced by operating_mode(), and reset_mode().
| #define MOD_STM 0x4 |
| #define NMSG_FIFO 27 |
| #define NMSG_FIFO2 28 |
| #define OCR 8 |
| #define PLL_CMD 12 |
Referenced by satcan_test().
| #define PLL_OFF 14 |
| #define PLL_RST 11 |
Referenced by satcan_test().
| #define PLL_STAT 13 |
| #define RAM_BASE 9 |
Referenced by satcan_test().
| #define RBSA 30 |
| #define RES 5 |
| #define RES2 10 |
| #define RMC 29 |
| #define RX 20 |
Referenced by satcan_test().
| #define RXERR 14 |
| #define RXFIFO_START 32 |
| #define SFF_D1 19 |
| #define SFF_D2 20 |
| #define SFF_D3 21 |
| #define SFF_D4 22 |
| #define SFF_D5 23 |
| #define SFF_D6 24 |
| #define SFF_D7 25 |
| #define SFF_D8 26 |
| #define SR 2 |
Referenced by can_read_eff(), can_send_eff(), and can_tx_complete().
| #define SR_BS 0x80 |
| #define SR_DOS 0x2 |
| #define SR_ES 0x40 |
| #define SR_RBS 0x1 |
Referenced by can_read_eff().
| #define SR_RS 0x10 |
| #define SR_TBS 0x4 |
Referenced by can_send_eff().
| #define SR_TCS 0x8 |
Referenced by can_tx_complete().
| #define SR_TS 0x20 |
| #define START_CTC 8 |
Referenced by satcan_test().
| #define STOP_CTC 10 |
| #define TST 9 |
| #define TXBUF_START 96 |
| #define TXERR 15 |
References BTR0, BTR1, can_filter(), CDR, IER, MOD, operating_mode(), and reset_mode().
Referenced by satcan_test().
| void* catch_interrupt | ( | void | func(), |
| int | irq | ||
| ) |
Referenced by satcan_test().
| disable_irq | ( | int | irqn | ) |
References irq_reg::mask.
| enable_irq | ( | int | irqn | ) |
References irq_reg::clear, and irq_reg::mask.
Referenced by satcan_test().
| force_irq | ( | int | irqn | ) |
References irq_reg::force.
| void oc_irq_handler | ( | int | irqn | ) |
References can_read_eff(), d, i, IR, and s.
Referenced by satcan_test().
| void operating_mode | ( | void | ) |
Referenced by can_init().
| void reset_mode | ( | void | ) |
Referenced by can_init().
| satcan_test | ( | unsigned int | sc_addr, |
| int | sc_irq, | ||
| unsigned int | oc_addr, | ||
| int | oc_irq, | ||
| unsigned int | mux_addr, | ||
| unsigned int | bus | ||
| ) |
References can_init(), catch_interrupt(), CDR, CMD0, CMD1, satcan_regs::ctrl, d, DATA, DMA, DMA_TX_1_CUR, DMA_TX_1_END, enable_irq(), INT_EN, irq_sc, satcan_regs::irqmask, irq_reg::level, satcan_regs::membase, oc_irq_handler(), PLL_CMD, PLL_RST, RAM_BASE, report_device(), RX, s, satcan_regs::satcan, sc_irq_handler(), and START_CTC.
| void sc_irq_handler | ( | int | irqn | ) |
References FIFO, i, irq_sc, satcan_regs::irqpend, and satcan_regs::satcan.
Referenced by satcan_test().
| volatile unsigned int d =0 |
Referenced by Irqmp::acknowledged_irq(), disable_irq_rt(), enable_irq_rt(), force_irq_rt(), gptimer_test(), grcan_test(), grhcan_test(), irqhandler_rt(), and main().
| volatile unsigned int irq_oc =0 |
| volatile unsigned int irq_sc =0 |
Referenced by satcan_test(), and sc_irq_handler().
| volatile unsigned char* mem |
Referenced by Memory::b_transport(), brm_1553_test(), find_ahb_slv(), Memory::Memory(), rt_1553_test(), and sc_main().
| volatile int oc_irq_done |
| volatile unsigned char* oc_reg |
| struct satcan_regs* r |
| volatile unsigned int s =0 |
Referenced by blit(), decode(), des_encrypt(), des_set_key(), huff_ac_dec(), huff_dc_dec(), trap::OSEmulator< issueWidth >::initSysCalls(), PythonModule::load(), main(), oc_irq_handler(), satcan_test(), sc_register_base::scireg_get_child_regions(), and sc_register_bank< unsigned int, unsigned int >::scireg_get_child_regions().
| volatile int sc_irq_done |