Logo SoCRocket

Transaction-Level Modeling Framework for Space Applications

Class List
Here are the classes, structs, unions and interfaces with brief descriptions:
[detail level 123456]
oNasync
oNbenchmarkProc
oNblas
oNcomments
oNcore
oNdoxycomment
oNdoxygen_preprocessor
oNenhancedtable
oNerror_handler
oNfilterprocessor
oNgetSpeedResults
oNklasses
oNlapack
oNleon3_funclt_trap
oNlog2db
oNpysc
oNregister
oNscireg_ns
oNsetup
oNshell
oNspeedGraph
oNsr_signal
oNstatemachine
oNtest1
oNtools
oNtranscript2db
oNtrap
oNusi
oNv
oNvirtualenv
oC_exitIntrinsic
oCahb_check_slave_type
oCAHBCtrl
oCAHBDeviceThis class is a base class for grlib models. It implements the device plug and play informations. Together with the AHBCtrl class it implements the plug and play feature of the grlib
oCAHBDeviceBase
oCAHBInDefinition of class AHBIn
oCAHBMaster
oCAHBMem
oCAHBOut
oCahbpp_type
oCAHBProf
oCAHBSlave
oCahbstat
oCAMBABasePlatform
oCambadev
oCapb_check_slave_type
oCAPBCtrl
oCAPBDeviceThis class is a base class for grlib models. It implements the device plug and play informations. Together with the APBBridge class it implements the plug and play feature of the grlib
oCAPBDeviceBase
oCapbpp_type
oCapbps2_regs
oCAPBSlave
oCAPBSlaveSocket
oCAPBUARTThis class is a TLM 2.0 Model of the Aeroflex Gaisler GRLIB APBUART. Further informations to the original VHDL Modle are available in the GRLIB IP Core User's Manual Section 16
oCArrayStorage
oCataregs
oCBAR
oCBaseMemory
oCBaseModule
oCbrm_irq_reg
oCbrm_regs
oCcache_if
oCcan_oc_extended
oCcctrltype
oCchmodIntrinsic
oCchownIntrinsic
oCCLKDevice
oCcloseIntrinsic
oCcomplex
oCcomplex32
oCConnectionThread
oCcreatIntrinsic
oCCTRL_REG
oCdcache_in_type
oCdcache_out_type
oCdcio_payload_extensionPayload extensions for TLM data cache target socket
oCdict
oCdivcase
oCdp3_type
oCdsu3regs
oCdup2Intrinsic
oCdupIntrinsic
oCdvectorcacheData cache implementation for TrapGen LEON3 simulator
oCehc_itd
oCehc_qh
oCehc_qtd
oCehcauxregs
oCehccoreregs
oCerrorIntrinsic
oCException
oCext_erase
oCFaultDectect_if
oCfilter
oCformat_s
oCfstatIntrinsic
oCgetenvIntrinsic
oCgetpidIntrinsic
oCgettimeofdayIntrinsic
oCGlobalMemory
oCGPCounterThis class implements an internal counter of a gptimer
oCgptimer
oCGPTimerThis class is a TLM 2.0 Model of the Aeroflex Gaisler GRLIB GPTimer. Further informations to the original VHDL Modle are available in the GRLIB IP Core User's Manual Section 37
oCgrpwm_caps
oCgrpwm_core_regs
oCgrpwm_pwm_regs
oCi2cmst_regs
oCi2cmstregs
oCi2cslv_regs
oCicache_in_type
oCicache_out_type
oCicdiag_in_type
oCicio_payload_extensionPayload extensions for TLM instruction cache target socket
oCInitiator
oCIntrinsicBase
oCIntrinsicManager
oCio_if
oCirq_reg
oCirqctrl
oCIrqGenerator
oCirqmp
oCIrqmp
oCirqmp_rst_stimuli
oCisattyIntrinsic
oCivectorcacheInstruction cache implementation for TrapGen LEON3 simulator
oCkillIntrinsic
oCl2regs
oCl2timers
oCLeon3Top-level class of the memory sub-system for the TrapGen LEON3 simulator
oCLEON3_GRPCI_Regs_Map
oCLeon3Processor
oClocalramLocal Scratchpad RAM
oClseekIntrinsic
oClstatIntrinsic
oCmainIntrinsic
oCMapStorage
oCMctrlThis class is an TLM 2.0 Model of the Aeroflex Gaisler GRLIB mctrl. Further informations to the original VHDL Modle are available in the GRLIB IP Core User's Manual Section 66
oCMDRDataSet
oCMDRModel
oCMDRModelIterator
oCMDRMultiIndex
oCMDRVector
oCmem_if
oCMEMDeviceThis class is a base class for memory models. It implements the device plug and play informations
oCMemoryThis class models a generic memory. Depending on the configuration it can be used as ROM, IO, SRAM or SDRAM, in conjunction with the SoCRocket MCTRL
oCMemoryPower
oCmmuMemory Management Unit (MMU) for TrapGen LEON3 simulator
oCmmu_cacheTop-level class of the memory sub-system for the TrapGen LEON3 simulator
oCmmu_cache_baseTop-level class of the memory sub-system for the TrapGen LEON3 simulator
oCmmu_cache_if
oCmmu_cache_wrapper
oCmmu_if
oCmsclogger
oCmulcase
oCnocache
oCnotifyIntrinsic
oCopenIntrinsic
oCpci_config
oCpci_config_access_functions
oCpci_res
oCPlatformIntrinsic
oCpowermonitor
oCprof_info
oCPyScModule
oCPyScObjectGenerator
oCPythonModule
oCrandomIntrinsic
oCreadIntrinsic
oCrecord
oCReliabilityCell
oCReliabilityManager
oCReportIO
oCrtable
oCsatcan_regs
oCsbrkIntrinsic
oCsc_foreign_module
oCsc_registerM is the access mode
oCsc_register< unsigned char, M >
oCsc_register< unsigned int, M >
oCsc_register< unsigned long long, M >
oCsc_register< unsigned short, M >
oCsc_register_b
oCsc_register_bank
oCsc_register_bank_base
oCsc_register_baseRegister
oCsc_register_field
oCsc_register_field_bT is the data type of the register that contains this field
oCsc_register_field_base
oCsc_rf_valuecode
oCsp3_type
oCspictrlregs
oCspimctrlregs
oCspwregs
oCsr_paramThe parameters, sr_param class, templated
oCsr_param< bool >Template specialization for sr_param<bool>
oCsr_param< char >Template specialization for sr_param<char>
oCsr_param< double >Template specialization for sr_param<double>
oCsr_param< float >Template specialization for sr_param<float>
oCsr_param< int >Template specialization for sr_param<int>
oCsr_param< int16_t >
oCsr_param< int64_t >
oCsr_param< long long >Template specialization for sr_param<long long int>
oCsr_param< sc_core::sc_event >Template specialization for sr_param< sc_event >
oCsr_param< sc_core::sc_time >Template specialization for sr_param< sc_time >
oCsr_param< sc_dt::sc_bigint< W > >Template specialization for sr_param< sc_bigint<W> >
oCsr_param< sc_dt::sc_biguint< W > >Template specialization for sr_param< sc_biguint<W> >
oCsr_param< sc_dt::sc_bit >Template specialization for sr_param< sc_bit >
oCsr_param< sc_dt::sc_int< W > >Template specialization for sr_param< sc_int<W> >
oCsr_param< sc_dt::sc_int_base >Template specialization for sr_param< sc_int_base >
oCsr_param< sc_dt::sc_logic >Template specialization for sr_param< sc_logic >
oCsr_param< sc_dt::sc_signed >Template specialization for sr_param< sc_signed >
oCsr_param< sc_dt::sc_uint< W > >Template specialization for sr_param< sc_uint<W> >
oCsr_param< sc_dt::sc_uint_base >Template specialization for sr_param< sc_uint_base >
oCsr_param< sc_dt::sc_unsigned >Template specialization for sr_param< sc_unsigned >
oCsr_param< signed char >Template specialization for sr_param<signed char>
oCsr_param< std::string >Template specialization for sr_param<std::string>
oCsr_param< std::vector< std::string > >
oCsr_param< uint64_t >
oCsr_param< unsigned char >Template specialization for sr_param<unsigned char>
oCsr_param< unsigned int >Template specialization for sr_param<unsigned int>
oCsr_param< unsigned long long >Template specialization for sr_param<unsigned long long int>
oCsr_param< unsigned short >Template specialization for sr_param<unsigned short>
oCsr_param_base
oCsr_param_tTemplate specialized base class for configuration parameters
oCsr_register
oCsr_register_amba_socket
oCsr_register_bank
oCsr_register_callback
oCsr_register_callback_base
oCsr_register_field
oCsr_report
oCsr_report_handler
oCSrModuleRegistry
oCstatIntrinsic
oCStorage
oCsvgactrlregs
oCsysconfIntrinsic
oCt_cache_data
oCt_cache_line
oCt_cache_tag
oCt_PTE_context
oCt_snoop
oCtable
oCTcpIO
oCtest8
oCtimeIntrinsic
oCtimerreg
oCtimesIntrinsic
oCTimingMonitor
oCtlb_adaptor
oCTop
oCuart_regs
oCudivcase
oCuhc_qh
oCuhc_td
oCuhcregs
oCunlinkIntrinsic
oCUSIBaseDelegate
oCUSIDelegate
oCusleepIntrinsic
oCutimesIntrinsic
oCvectorcacheVirtual cache model, contain common functionality of instruction and data cache
\CwriteIntrinsic