Memory Management Unit (MMU) for TrapGen LEON3 simulator. More...

#include <mmu.h>

Inheritance diagram for mmu:

Collaboration diagram for mmu:

Public Member Functions
	GC_HAS_CALLBACKS ()

	mmu (ModuleName name, mmu_cache_if *_mmu_cache, unsigned int itlbnum, unsigned int dtlbnum, unsigned int tlb_type, unsigned int tlb_rep, unsigned int mmupgsz, bool pow_mon=false)
	Constructor of the Memory Management Unit. More...

	~mmu ()
	Destructor. More...

signed	tlb_lookup (unsigned int addr, unsigned asi, std::map< t_VAT, t_PTE_context > tlb, unsigned int tlb_size, sc_core::sc_time t, unsigned int debug, bool is_dbg, bool &cacheable, unsigned is_write, uint64_t paddr)
	Page descriptor cache (PDC) lookup. More...

unsigned int	read_mcr ()
	Read mmu control register (ASI 0x19) More...

unsigned int	read_mctpr ()
	Read mmu context pointer register (ASI 0x19) More...

unsigned int	read_mctxr ()
	Read mmu context register (ASI 0x19) More...

unsigned int	read_mfsr ()
	Read mmu fault status register (ASI 0x19) More...

unsigned int	read_mfar ()
	Read mmu fault address register (ASI 0x19) More...

void	write_mcr (unsigned int *data)
	Write mmu control register (ASI 0x19) More...

void	write_mctpr (unsigned int *data)
	Write mmu context pointer register (ASI 0x19) More...

void	write_mctxr (unsigned int *data)
	Write mmu context register (ASI 0x19) More...

void	diag_read_itlb (unsigned int addr, unsigned int *data)
	Diagnostic read of instruction PDC (ASI 0x5) More...

void	diag_write_itlb (unsigned int addr, unsigned int *data)
	Diagnostic write of instruction PDC (ASI 0x5) More...

void	diag_read_dctlb (unsigned int addr, unsigned int *data)
	Diagnostic read of data PDC or shared instruction and data PDC (ASI 0x6) More...

void	diag_write_dctlb (unsigned int addr, unsigned int *data)
	Diagnostic write of data PDC or shared instruction and data PDC (ASI 0x6) More...

unsigned int	tlb_remove (std::map< t_VAT, t_PTE_context > *tlb, unsigned int tlb_size)

void	lru_update (t_VAT vpn, std::map< t_VAT, t_PTE_context > *tlb, unsigned int tlb_size)
	LRU replacement history updater. More...

tlb_adaptor *	get_itlb_if ()
	Return pointer to tlb instruction interface. More...

tlb_adaptor *	get_dtlb_if ()
	Return pointer to tlb data interface. More...

void	start_of_simulation ()
	Automatically started at beginning of simulation. More...

void	power_model ()
	Calculate power/energy values from normalized input data. More...

void	tlb_flush ()
	TLB flush complete. More...

void	tlb_flush (uint32_t vpn)
	TLB flush certain entry. More...

gs::cnf::callback_return_type	sta_power_cb (gs::gs_param_base &changed_param, gs::cnf::callback_type reason)
	Static power callback. More...

gs::cnf::callback_return_type	int_power_cb (gs::gs_param_base &changed_param, gs::cnf::callback_type reason)
	Dynamic/Internal power callback. More...

gs::cnf::callback_return_type	swi_power_cb (gs::gs_param_base &changed_param, gs::cnf::callback_type reason)
	Dynamic/Switching power callback. More...

void	end_of_simulation ()
	Displays execution statistics at the end of the simulation. More...

void	clkcng (sc_core::sc_time &clk)
	Helper functions for definition of clock cycle. More...

Public Member Functions inherited from mmu_if
virtual	~mmu_if ()

Public Attributes
mmu_cache_if *	m_mmu_cache
	pointer to mmu_cache module (ahb interface functions) More...

tlb_adaptor *	itlb_adaptor
	pointer to instruction tlb adaptor More...

tlb_adaptor *	dtlb_adaptor
	pointer to data tlb adaptor More...

std::map< t_VAT, t_PTE_context > *	itlb
	associative memory for instruction TLB (eventually also data tlb in shared mode) More...

std::map< t_VAT, t_PTE_context > *	dtlb
	associative memory for data TLB (not used in shared mode) More...

std::map< t_VAT, t_PTE_context > ::iterator	pdciter
	iterator for PDC lookup More...

t_PTE_context *	m_current_PTE_context
	helper for tlb handling More...

unsigned int	MMU_CONTROL_REG

unsigned int	MMU_CONTEXT_TABLE_POINTER_REG

unsigned int	MMU_CONTEXT_REG

unsigned int	MMU_FAULT_STATUS_REG

unsigned int	MMU_FAULT_ADDRESS_REG

unsigned int	m_itlbnum
	number of instruction tlbs More...

unsigned int	m_dtlbnum
	number of data tlbs More...

unsigned int	m_itlblog2
	log2 version of itlbnum More...

unsigned int	m_dtlblog2
	log2 version of dtlbnum More...

unsigned int	m_tlb_type
	tlb type (bit0 - split/combined, bit1 - standard/fast write buffer) More...

unsigned int	m_tlb_rep
	tlb replacment strategy (no inform. found yet - tmp use random) More...

unsigned int	m_mmupgsz
	mmu page size More...

unsigned int	m_idx1
	width of vtag index 1 More...

unsigned int	m_idx2
	width of vtag index 2 More...

unsigned int	m_idx3
	width of vtag index 3 More...

unsigned int	m_vtag_width
	total width of vtag More...

uint32_t	m_pseudo_rand
	Pseudo random counter for LRU. More...

bool	m_pow_mon
	Power Monitoring enabled? More...

unsigned	access_table [8][8]

gs::cnf::cnf_api *	m_api
	GreenControl API container. More...

gs::gs_param_array	m_performance_counters
	Open a namespace for performance counting in the greencontrol realm. More...

gs::gs_param< unsigned long long * >	tihits
	Number of TLB hits. More...

gs::gs_param< unsigned long long * >	tdhits

sr_param< uint64_t >	timisses
	Number of TLB misses. More...

sr_param< uint64_t >	tdmisses

sr_param< double >	sta_power_norm
	Normalized static power of mmu. More...

sr_param< double >	int_power_norm
	Normalized internal power of mmu (switching independent) More...

sr_param< double >	sta_tlb_power_norm
	Normalized tlb static power input. More...

sr_param< double >	int_tlb_power_norm
	Normalized internal power of tlb. More...

sr_param< double >	dyn_tlb_read_energy_norm
	Normalized tlb read energy. More...

sr_param< double >	dyn_tlb_write_energy_norm
	Normalized tlb write energy. More...

gs::gs_param_array	power
	Parameter array for power data output. More...

sr_param< double >	sta_power
	MMU static power. More...

sr_param< double >	int_power
	MMU internal power. More...

sr_param< double >	swi_power
	MMU switching power. More...

sr_param< sc_core::sc_time >	power_frame_starting_time
	Power frame starting time. More...

gs::gs_param_array	itlbram
	Parameter array for power output of itlb. More...

sr_param< double >	dyn_itlb_read_energy
	Dynamic energy itlb read. More...

sr_param< double >	dyn_itlb_write_energy
	Dynamic energy itlb write. More...

sr_param< uint64_t >	dyn_itlb_reads
	Number of itlb reads. More...

sr_param< uint64_t >	dyn_itlb_writes
	Number of itlb writes. More...

gs::gs_param_array	dtlbram
	Parameter array for power output of dtlb. More...

sr_param< double >	dyn_dtlb_read_energy
	Dynamic energy dtlb read. More...

sr_param< double >	dyn_dtlb_write_energy
	Dynamic energy dtlb write. More...

sr_param< uint64_t >	dyn_dtlb_reads
	Number of dtlb reads. More...

sr_param< uint64_t >	dyn_dtlb_writes
	Number of dtlb writes. More...

sc_core::sc_time	clockcycle
	Clock cycle time. More...

Detailed Description

Memory Management Unit (MMU) for TrapGen LEON3 simulator.

Member Function Documentation

mmu::GC_HAS_CALLBACKS ( )

Member Data Documentation

unsigned mmu::access_table[8][8]

Referenced by mmu().

sc_core::sc_time mmu::clockcycle

Clock cycle time.

Referenced by clkcng(), and power_model().

std::map<t_VAT, t_PTE_context>* mmu::dtlb

associative memory for data TLB (not used in shared mode)

Referenced by diag_read_dctlb(), mmu(), and tlb_flush().

tlb_adaptor* mmu::dtlb_adaptor

pointer to data tlb adaptor

Referenced by get_dtlb_if(), and mmu().

gs::gs_param_array mmu::dtlbram

Parameter array for power output of dtlb.

sr_param<double> mmu::dyn_dtlb_read_energy

Dynamic energy dtlb read.

Referenced by power_model(), and swi_power_cb().

sr_param<uint64_t> mmu::dyn_dtlb_reads

Number of dtlb reads.

Referenced by swi_power_cb().

sr_param<double> mmu::dyn_dtlb_write_energy

Dynamic energy dtlb write.

Referenced by power_model(), and swi_power_cb().

sr_param<uint64_t> mmu::dyn_dtlb_writes

Number of dtlb writes.

Referenced by swi_power_cb(), and tlb_lookup().

sr_param<double> mmu::dyn_itlb_read_energy

Dynamic energy itlb read.

Referenced by power_model(), and swi_power_cb().

sr_param<uint64_t> mmu::dyn_itlb_reads

Number of itlb reads.

Referenced by swi_power_cb().

sr_param<double> mmu::dyn_itlb_write_energy

Dynamic energy itlb write.

Referenced by power_model(), and swi_power_cb().

sr_param<uint64_t> mmu::dyn_itlb_writes

Number of itlb writes.

Referenced by swi_power_cb(), and tlb_lookup().

sr_param<double> mmu::dyn_tlb_read_energy_norm

Normalized tlb read energy.

Referenced by power_model().

sr_param<double> mmu::dyn_tlb_write_energy_norm

Normalized tlb write energy.

Referenced by power_model().

sr_param<double> mmu::int_power

MMU internal power.

Referenced by mmu(), and power_model().

sr_param<double> mmu::int_power_norm

Normalized internal power of mmu (switching independent)

Referenced by power_model().

sr_param<double> mmu::int_tlb_power_norm

Normalized internal power of tlb.

Referenced by power_model().

std::map<t_VAT, t_PTE_context>* mmu::itlb

associative memory for instruction TLB (eventually also data tlb in shared mode)

Referenced by diag_read_itlb(), mmu(), tlb_flush(), and tlb_lookup().

tlb_adaptor* mmu::itlb_adaptor

pointer to instruction tlb adaptor

Referenced by get_itlb_if(), and mmu().

gs::gs_param_array mmu::itlbram

Parameter array for power output of itlb.

gs::cnf::cnf_api* mmu::m_api

GreenControl API container.

Referenced by mmu().

t_PTE_context* mmu::m_current_PTE_context

helper for tlb handling

unsigned int mmu::m_dtlblog2

log2 version of dtlbnum

Referenced by mmu().

unsigned int mmu::m_dtlbnum

number of data tlbs

Referenced by end_of_simulation(), mmu(), and power_model().

unsigned int mmu::m_idx1

width of vtag index 1

Referenced by mmu().

unsigned int mmu::m_idx2

width of vtag index 2

Referenced by mmu().

unsigned int mmu::m_idx3

width of vtag index 3

Referenced by mmu().

unsigned int mmu::m_itlblog2

log2 version of itlbnum

Referenced by mmu().

unsigned int mmu::m_itlbnum

number of instruction tlbs

Referenced by end_of_simulation(), mmu(), and power_model().

mmu_cache_if* mmu::m_mmu_cache

pointer to mmu_cache module (ahb interface functions)

Referenced by tlb_lookup().

unsigned int mmu::m_mmupgsz

mmu page size

gs::gs_param_array mmu::m_performance_counters

Open a namespace for performance counting in the greencontrol realm.

bool mmu::m_pow_mon

Power Monitoring enabled?

Referenced by mmu(), start_of_simulation(), and tlb_lookup().

uint32_t mmu::m_pseudo_rand

Pseudo random counter for LRU.

Referenced by tlb_remove().

unsigned int mmu::m_tlb_rep

tlb replacment strategy (no inform. found yet - tmp use random)

Referenced by tlb_remove().

unsigned int mmu::m_tlb_type

tlb type (bit0 - split/combined, bit1 - standard/fast write buffer)

Referenced by end_of_simulation(), mmu(), and power_model().

unsigned int mmu::m_vtag_width

total width of vtag

Referenced by diag_read_dctlb(), diag_read_itlb(), mmu(), and tlb_lookup().

unsigned int mmu::MMU_CONTEXT_REG

MMU Context Number (Page 255 Sparc Ref Manual):
--------------------------------------------—
The Context Register defines which of the possible process virtual address spaces is considered the current address space. Subsequently accesses to memory through the MMU are translated for the current address space, until the Context Register is changed. Each MMU implementation may specify a maximum context number, which must be one less than a power of 2.
[31-0] Context Number

Referenced by mmu(), read_mctxr(), tlb_lookup(), and write_mctxr().

unsigned int mmu::MMU_CONTEXT_TABLE_POINTER_REG

MMU Context Table Pointer (Page 254 Sparc Ref Manual):
---------------------------------------------------—
The Context Table Pointer points to the Context Table in physical memory. The table is indexed by the contents of the Context Register. The Context Table Pointer appears on bits 35 through 6 of the physical address bus during the first fetch occurring during miss processing. The context table pointed to by the Context Table Pointer must be aligned on a boundary equal to the size of the table.
[31-2] Context Table Pointer

Referenced by mmu(), read_mctpr(), and write_mctpr().

unsigned int mmu::MMU_CONTROL_REG

MMU Control Register (Page 253 Sparc Ref Manual):
----------------------------------------------—
[31-28] IMPL - Identifies the specific implementation of the MMU. It is hardwired into the implementation and is read only (0000).
[27-24] VER - Version of the MMU implementation (0001)(read-only)
[32-21] ITLB - Number of ITLB entries. The number of ITLB entries is
calculated as 2^ITLB. If the TLB is shared between instructions and data,
this field indicates the total number of TLBs. [20-18] DTLB - Number of DTLB entries. The number of DTLB entries is
calculated as 2^DTLB. If the TLB is shared between instructions and data,
this field is zero. [17-16] Page size.The size of the smallest MMU page: 0 - 4kbyte, 1 - 8kbyte,
2 - 16kbyte, 3 - 32kbyte. [15] TLB disable. When set to 1, the TLB will be disabled and each data
access will generate an MMU page table walk.
[14] Separate TLB. This bit is set to 1 if separate instructions
and data TLM are implemented.
[13-2] reserved
[1] NF - The "No Fault" bit. When NF=0, any fault detected by the MMU causes FSR and FAR to be updated and causes a fault to be generated to the processor. When NF=1, a fault on an access to ASI 9 is handled as when NF=0; a fault on an access to any other ASI causes FSR and FAR to be updated but no fault is generated to the processor. If a fault on access to an ASI other than 9 occurs while NF=1, subsequently resetting NF from 1 to 0 does not cause a fault to the processor (even though FSR.FT != 0 at that time). A change in value of the NF bit takes effect as soon as the bit is written; a subsequent access to ASI 9 will be evaluated according to the new value of the NF bit.
[0] E - The Enable bit enables (1) or disables (0) the MMU. When the MMU is disabled:

All virtual addresses pass through the MMU untranslated and appear as physical addresses.
The upper 4 of the 36 bits of the physical address are zero.
The MMU indicates that all virtual addresses are non-cacheable

Referenced by mmu(), read_mcr(), tlb_lookup(), and write_mcr().

unsigned int mmu::MMU_FAULT_ADDRESS_REG

MMU Fault Address Register (Page 258 Sparc Ref Manual):
----------------------------------------------------—
The Fault Address Register contains the virtual memory address of the fault recorded in the Fault Status Register. Fault addresses are overwritten according to the same priority used for the Fault Status Register. Writes to the Fault Address Register are ignored.
[31-0] Fault Address

Referenced by mmu(), read_mfar(), and tlb_lookup().

unsigned int mmu::MMU_FAULT_STATUS_REG

MMU Fault Status Register (Page 256 Sparc Ref Manual):
---------------------------------------------------—
The Fault Status Register provides information on exceptions (faults) issued by the MMU. Since the CPU is pipelined, several faults may occur before a trap is taken. The faults are grouped into three classes:

instruction access faults
data access faults
translation table access faults
If another instruction access fault occurs before the fault status of a previous instruction access fault has been read by the CPU, the MMU writes the status of the latest fault into the Fault Status Register,writes the faulting address into the Fault Address Register, and sets the OW bit to indicate that the previous fault status has been lost. The MMU and CPU must ensure that if multiple data access faults can occur, only the status of the one taken by the CPU is latched into the Fault Status Register. If data fault status overwrites previous instruciton fault status, the overwrite bit (OW) is cleared, since the fault status is represented correctly. An instruciton access fault may not overwrite a data access fault. A translation table access fault occurs if an MMU page table access causes an external system error. If a translation table access fault overwrites a previous instruction or data access fault, the OW bit is cleared. An instruction or data access fault may not overwrite a translation table access fault.
[17-10] EBE - External Bus Error field bits are set when a system error occurs during memory access. The meaning of the individual bits are implementation-dependent.
External Bus Errors are time-outs, parity errors e.g.. Not supported by TLM model.
[9-8] L - The Level field is set to the page table level of the entry which caused the fault (0 - Context Table, 1 - Level 1 Page Table, 2 - Level 2, 3 - Level 3).
[7-5] AT - The Access Type field defines the taype of access which cause the fault. (see Page 257 of Sparc Ref Manual)
[4-2] FT - Defines the Fault Type of the current fault. (see Page 257 of Sparc Ref Man.)
[1] FAV - The Fault Address Valid bit is set to one if the contents of the Fault Address Register are valid.
[0] OW - The Overwrite bit is set to one if the Fault Status Register has been written more than once by faults of the same class since the last time it was read.

Referenced by mmu(), read_mfsr(), and tlb_lookup().

std::map<t_VAT, t_PTE_context>::iterator mmu::pdciter

iterator for PDC lookup

Referenced by diag_read_dctlb(), and diag_read_itlb().

gs::gs_param_array mmu::power

Parameter array for power data output.

sr_param<sc_core::sc_time> mmu::power_frame_starting_time

Power frame starting time.

Referenced by swi_power_cb().

sr_param<double> mmu::sta_power

MMU static power.

Referenced by mmu(), and power_model().