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Transaction-Level Modeling Framework for Space Applications

Classes | Namespaces | Macros
instructions.hpp File Reference
#include "core/common/trapgen/instructionBase.hpp"
#include <string>
#include "core/common/trapgen/utils/customExceptions.hpp"
#include "core/common/trapgen/utils/trap_utils.hpp"
#include "gaisler/leon3/intunit/registers.hpp"
#include "gaisler/leon3/intunit/alias.hpp"
#include "gaisler/leon3/intunit/memory.hpp"
#include "gaisler/leon3/intunit/externalPins.hpp"
#include <sstream>
#include "core/common/systemc.h"
Include dependency graph for instructions.hpp:
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Classes

class  leon3_funclt_trap::Instruction
 
class  leon3_funclt_trap::WB_plain_op
 
class  leon3_funclt_trap::ICC_writeLogic_op
 
class  leon3_funclt_trap::ICC_writeTSub_op
 
class  leon3_funclt_trap::ICC_writeDiv_op
 
class  leon3_funclt_trap::ICC_writeAdd_op
 
class  leon3_funclt_trap::ICC_writeSub_op
 
class  leon3_funclt_trap::ICC_writeTAdd_op
 
class  leon3_funclt_trap::ICC_writeTVSub_op
 
class  leon3_funclt_trap::WB_tv_op
 
class  leon3_funclt_trap::ICC_writeTVAdd_op
 
class  leon3_funclt_trap::InvalidInstr
 
class  leon3_funclt_trap::READasr
 
class  leon3_funclt_trap::WRITEY_reg
 
class  leon3_funclt_trap::XNOR_reg
 
class  leon3_funclt_trap::ANDNcc_reg
 
class  leon3_funclt_trap::LDSB_imm
 
class  leon3_funclt_trap::WRITEpsr_imm
 
class  leon3_funclt_trap::READy
 
class  leon3_funclt_trap::XNORcc_reg
 
class  leon3_funclt_trap::READpsr
 
class  leon3_funclt_trap::ANDN_imm
 
class  leon3_funclt_trap::ANDcc_reg
 
class  leon3_funclt_trap::TSUBcc_imm
 
class  leon3_funclt_trap::LDSBA_reg
 
class  leon3_funclt_trap::LDUH_imm
 
class  leon3_funclt_trap::STA_reg
 
class  leon3_funclt_trap::ORN_reg
 
class  leon3_funclt_trap::LDSHA_reg
 
class  leon3_funclt_trap::STBA_reg
 
class  leon3_funclt_trap::ST_imm
 
class  leon3_funclt_trap::READtbr
 
class  leon3_funclt_trap::UDIVcc_imm
 
class  leon3_funclt_trap::SWAPA_reg
 
class  leon3_funclt_trap::ADDXcc_imm
 
class  leon3_funclt_trap::STB_imm
 
class  leon3_funclt_trap::SUBXcc_imm
 
class  leon3_funclt_trap::STH_reg
 
class  leon3_funclt_trap::SRL_imm
 
class  leon3_funclt_trap::WRITEasr_imm
 
class  leon3_funclt_trap::UMULcc_reg
 
class  leon3_funclt_trap::LDSTUB_reg
 
class  leon3_funclt_trap::XOR_imm
 
class  leon3_funclt_trap::SMAC_reg
 
class  leon3_funclt_trap::WRITEasr_reg
 
class  leon3_funclt_trap::LD_reg
 
class  leon3_funclt_trap::ST_reg
 
class  leon3_funclt_trap::SUBcc_reg
 
class  leon3_funclt_trap::LDD_reg
 
class  leon3_funclt_trap::ADDcc_imm
 
class  leon3_funclt_trap::LDUH_reg
 
class  leon3_funclt_trap::SRL_reg
 
class  leon3_funclt_trap::SAVE_imm
 
class  leon3_funclt_trap::MULScc_reg
 
class  leon3_funclt_trap::OR_imm
 
class  leon3_funclt_trap::STD_imm
 
class  leon3_funclt_trap::SUBXcc_reg
 
class  leon3_funclt_trap::ADDX_imm
 
class  leon3_funclt_trap::SWAP_imm
 
class  leon3_funclt_trap::UMUL_reg
 
class  leon3_funclt_trap::WRITEY_imm
 
class  leon3_funclt_trap::AND_reg
 
class  leon3_funclt_trap::FLUSH_imm
 
class  leon3_funclt_trap::SRA_reg
 
class  leon3_funclt_trap::STH_imm
 
class  leon3_funclt_trap::WRITEwim_imm
 
class  leon3_funclt_trap::LDD_imm
 
class  leon3_funclt_trap::SLL_imm
 
class  leon3_funclt_trap::LDUHA_reg
 
class  leon3_funclt_trap::TADDcc_reg
 
class  leon3_funclt_trap::TADDcc_imm
 
class  leon3_funclt_trap::SDIV_imm
 
class  leon3_funclt_trap::TSUBccTV_imm
 
class  leon3_funclt_trap::FLUSH_reg
 
class  leon3_funclt_trap::ORNcc_reg
 
class  leon3_funclt_trap::RETT_imm
 
class  leon3_funclt_trap::SDIVcc_reg
 
class  leon3_funclt_trap::ADD_reg
 
class  leon3_funclt_trap::TRAP_imm
 
class  leon3_funclt_trap::WRITEtbr_imm
 
class  leon3_funclt_trap::LDUB_reg
 
class  leon3_funclt_trap::RESTORE_reg
 
class  leon3_funclt_trap::ADDXcc_reg
 
class  leon3_funclt_trap::STB_reg
 
class  leon3_funclt_trap::AND_imm
 
class  leon3_funclt_trap::SMUL_imm
 
class  leon3_funclt_trap::ADD_imm
 
class  leon3_funclt_trap::UMUL_imm
 
class  leon3_funclt_trap::READwim
 
class  leon3_funclt_trap::LDSTUB_imm
 
class  leon3_funclt_trap::SMAC_imm
 
class  leon3_funclt_trap::LDSB_reg
 
class  leon3_funclt_trap::ANDN_reg
 
class  leon3_funclt_trap::TSUBccTV_reg
 
class  leon3_funclt_trap::SETHI
 
class  leon3_funclt_trap::SRA_imm
 
class  leon3_funclt_trap::LDSH_reg
 
class  leon3_funclt_trap::UDIVcc_reg
 
class  leon3_funclt_trap::ORN_imm
 
class  leon3_funclt_trap::STD_reg
 
class  leon3_funclt_trap::ANDNcc_imm
 
class  leon3_funclt_trap::TADDccTV_imm
 
class  leon3_funclt_trap::WRITEtbr_reg
 
class  leon3_funclt_trap::SUBX_reg
 
class  leon3_funclt_trap::XNOR_imm
 
class  leon3_funclt_trap::UDIV_imm
 
class  leon3_funclt_trap::LDSH_imm
 
class  leon3_funclt_trap::UNIMP
 
class  leon3_funclt_trap::LDSTUBA_reg
 
class  leon3_funclt_trap::UMULcc_imm
 
class  leon3_funclt_trap::ORcc_reg
 
class  leon3_funclt_trap::MULScc_imm
 
class  leon3_funclt_trap::XORcc_reg
 
class  leon3_funclt_trap::SUB_reg
 
class  leon3_funclt_trap::WRITEwim_reg
 
class  leon3_funclt_trap::UMAC_imm
 
class  leon3_funclt_trap::TSUBcc_reg
 
class  leon3_funclt_trap::BRANCH
 
class  leon3_funclt_trap::SMULcc_reg
 
class  leon3_funclt_trap::SUB_imm
 
class  leon3_funclt_trap::ADDcc_reg
 
class  leon3_funclt_trap::XOR_reg
 
class  leon3_funclt_trap::SUBcc_imm
 
class  leon3_funclt_trap::TADDccTV_reg
 
class  leon3_funclt_trap::SDIV_reg
 
class  leon3_funclt_trap::SMULcc_imm
 
class  leon3_funclt_trap::SWAP_reg
 
class  leon3_funclt_trap::SUBX_imm
 
class  leon3_funclt_trap::STDA_reg
 
class  leon3_funclt_trap::UMAC_reg
 
class  leon3_funclt_trap::JUMP_imm
 
class  leon3_funclt_trap::SMUL_reg
 
class  leon3_funclt_trap::XORcc_imm
 
class  leon3_funclt_trap::ORNcc_imm
 
class  leon3_funclt_trap::LDUBA_reg
 
class  leon3_funclt_trap::JUMP_reg
 
class  leon3_funclt_trap::ADDX_reg
 
class  leon3_funclt_trap::UDIV_reg
 
class  leon3_funclt_trap::XNORcc_imm
 
class  leon3_funclt_trap::STBAR
 
class  leon3_funclt_trap::LDA_reg
 
class  leon3_funclt_trap::STHA_reg
 
class  leon3_funclt_trap::LDDA_reg
 
class  leon3_funclt_trap::SLL_reg
 
class  leon3_funclt_trap::RESTORE_imm
 
class  leon3_funclt_trap::LD_imm
 
class  leon3_funclt_trap::TRAP_reg
 
class  leon3_funclt_trap::LDUB_imm
 
class  leon3_funclt_trap::RETT_reg
 
class  leon3_funclt_trap::SDIVcc_imm
 
class  leon3_funclt_trap::SAVE_reg
 
class  leon3_funclt_trap::OR_reg
 
class  leon3_funclt_trap::ORcc_imm
 
class  leon3_funclt_trap::CALL
 
class  leon3_funclt_trap::WRITEpsr_reg
 
class  leon3_funclt_trap::ANDcc_imm
 
class  leon3_funclt_trap::IRQ_IRQ_Instruction
 

Namespaces

 leon3_funclt_trap
 

Macros

#define FUNC_MODEL
 
#define LT_IF
 
#define RESET   0
 
#define DATA_STORE_ERROR   1
 
#define INSTR_ACCESS_MMU_MISS   2
 
#define INSTR_ACCESS_ERROR   3
 
#define R_REGISTER_ACCESS_ERROR   4
 
#define INSTR_ACCESS_EXC   5
 
#define PRIVILEDGE_INSTR   6
 
#define ILLEGAL_INSTR   7
 
#define FP_DISABLED   8
 
#define CP_DISABLED   9
 
#define UNIMPL_FLUSH   10
 
#define WATCHPOINT_DETECTED   11
 
#define WINDOW_OVERFLOW   12
 
#define WINDOW_UNDERFLOW   13
 
#define MEM_ADDR_NOT_ALIGNED   14
 
#define FP_EXCEPTION   15
 
#define CP_EXCEPTION   16
 
#define DATA_ACCESS_ERROR   17
 
#define DATA_ACCESS_MMU_MISS   18
 
#define DATA_ACCESS_EXC   19
 
#define TAG_OVERFLOW   20
 
#define DIV_ZERO   21
 
#define TRAP_INSTRUCTION   22
 
#define IRQ_LEV_15   23
 
#define IRQ_LEV_14   24
 
#define IRQ_LEV_13   25
 
#define IRQ_LEV_12   26
 
#define IRQ_LEV_11   27
 
#define IRQ_LEV_10   28
 
#define IRQ_LEV_9   29
 
#define IRQ_LEV_8   30
 
#define IRQ_LEV_7   31
 
#define IRQ_LEV_6   32
 
#define IRQ_LEV_5   33
 
#define IRQ_LEV_4   34
 
#define IRQ_LEV_3   35
 
#define IRQ_LEV_2   36
 
#define IRQ_LEV_1   37
 
#define IMPL_DEP_EXC   38
 
#define MULT_SIZE_16
 

Macro Definition Documentation

#define CP_DISABLED   9
#define CP_EXCEPTION   16
#define DATA_ACCESS_ERROR   17
#define DATA_ACCESS_EXC   19
#define DATA_ACCESS_MMU_MISS   18
#define DATA_STORE_ERROR   1
#define DIV_ZERO   21
#define FP_DISABLED   8
#define FP_EXCEPTION   15
#define FUNC_MODEL
#define ILLEGAL_INSTR   7
#define IMPL_DEP_EXC   38
#define INSTR_ACCESS_ERROR   3
#define INSTR_ACCESS_EXC   5
#define INSTR_ACCESS_MMU_MISS   2
#define IRQ_LEV_1   37
#define IRQ_LEV_10   28
#define IRQ_LEV_11   27
#define IRQ_LEV_12   26
#define IRQ_LEV_13   25
#define IRQ_LEV_14   24
#define IRQ_LEV_15   23
#define IRQ_LEV_2   36
#define IRQ_LEV_3   35
#define IRQ_LEV_4   34
#define IRQ_LEV_5   33
#define IRQ_LEV_6   32
#define IRQ_LEV_7   31
#define IRQ_LEV_8   30
#define IRQ_LEV_9   29
#define LT_IF
#define MEM_ADDR_NOT_ALIGNED   14
#define MULT_SIZE_16
#define PRIVILEDGE_INSTR   6
#define R_REGISTER_ACCESS_ERROR   4
#define RESET   0
#define TAG_OVERFLOW   20
#define TRAP_INSTRUCTION   22
#define UNIMPL_FLUSH   10
#define WATCHPOINT_DETECTED   11
#define WINDOW_OVERFLOW   12
#define WINDOW_UNDERFLOW   13