One oft the goals were to develop several TLM IP models. All mandatory IP models:

Name	Description
AHBCtrl	Aeroflex Gaisler AMBA AHB Controler
MCtrl	Aeroflex Gaisler GRLIB MCTRL Memory Controller or equivalent
Memory	A memory model working with IP 2
MMU Cache	A Harvard L1 cache (including support of cache coherence protocols, snooping and write invalidate) and a SPARCv8 MMU or equivalent
GPTimer	Aeroflex Gaisler GPTIMER General Purpose Timer Unit or equivalent
IRQMP	Aeroflex Gaisler IRQMP Interrupt Controller or equivalent
AHBSpaceWire	A module which integrates the CSpaceWire Model and the SoCRocket Framework

In addition the following supplementary IP models where designed to make the platform simulation more accurate and usable:

Name	Description
APBCtrl	AMBA AHB to APB Bridge
AHBMem	Aeroflex Gaisler GRLIB AHB Memory
APBUART	Aeroflex Gaisler GRLIB APBUART
AHBProf	SystemC AHB System Profiler

On top of that the following IP models were build for lecturing purpose:

Name	Description
AHBIn	A simple AHB Inut Device to demonstrate how to build a AHB Master
AHBOut	A Device that demonstrates how to build a simple AHB Slave