Transaction-Level Modeling Framework for Space Applications
virtual cache model, contain common functionality of instruction and data cache More...
#include <vectorcache.h>
Public Member Functions | |
Interface Data Methods | |
virtual bool | mem_read (unsigned int address, unsigned int asi, unsigned char *data, unsigned int len, sc_core::sc_time *t, unsigned int *debug, bool is_dbg, bool &cacheable, bool is_lock) |
Read from cache. More... | |
virtual void | mem_write (unsigned int address, unsigned int asi, unsigned char *data, unsigned int len, sc_core::sc_time *t, unsigned int *debug, bool is_dbg, bool &cacheable, bool is_lock) |
Write through cache. More... | |
Interface Control Methods | |
Interface Data Methods | |
virtual unsigned int | read_config_reg (sc_core::sc_time *t) |
Read cache configuration register (ASI 0x2) More... | |
virtual void | read_cache_tag (unsigned int address, unsigned int *data, sc_core::sc_time *t) |
Read data cache tags (ASI 0xe) More... | |
virtual void | write_cache_tag (unsigned int address, unsigned int *data, sc_core::sc_time *t) |
Write data cache tags (ASI 0xe) More... | |
virtual void | read_cache_entry (unsigned int address, unsigned int *data, sc_core::sc_time *t) |
Read data cache entries/data (ASI 0xf) More... | |
virtual void | write_cache_entry (unsigned int address, unsigned int *data, sc_core::sc_time *t) |
Write data cache entries/data (ASI 0xf) More... | |
virtual void | flush (sc_core::sc_time *t, unsigned int *debug, bool is_dbg) |
Flush cache. More... | |
virtual void | snoop_invalidate (const t_snoop &snoop, const sc_core::sc_time &delay) |
Snooping function (invalidates cache line(s)) More... | |
Diagnostic Methods | |
Internal Methods | |
virtual unsigned int | check_mode ()=0 |
Returns the mode bits of the cache. More... | |
virtual t_cache_type | get_cache_type ()=0 |
Returns type of cache implementing this interface. More... | |
virtual void | dbg_out (unsigned int line) |
Display of cache lines for debug. More... | |
void | clkcng (sc_core::sc_time &clk) |
Helper functions for definition of clock cycle. More... | |
Public Member Functions inherited from cache_if | |
virtual | ~cache_if () |
Public Member Functions inherited from mem_if | |
virtual | ~mem_if () |
Protected Member Functions | |
Internal Methods | |
Interface Control Methods | |
unsigned | get_tag (unsigned address) |
Address parsing one-liners. More... | |
unsigned | get_idx (unsigned address) |
unsigned | get_offset (unsigned address) |
unsigned | get_address (unsigned tag, unsigned idx, unsigned offset) |
unsigned int | offset2valid (unsigned int offset, unsigned int len=4) |
Transforms a cache-line offset into a valid mask. More... | |
unsigned int | replacement_selector (unsigned int idx, unsigned int mode) |
Returns number of the way to be refilled - depending on replacement strategy. More... | |
void | lru_update (unsigned int idx, unsigned int set_select) |
Updates the lru counters for every cache hit. More... | |
void | lrr_update (unsigned int idx, unsigned int set_select) |
Updates the lrr bits for every line replacement. More... | |
std::vector< t_cache_line > ::iterator | lookup_line (unsigned idx, unsigned way) |
int | locate_line (unsigned const tag, unsigned const idx, unsigned const offset, unsigned const len, sc_core::sc_time *delay) |
More... | |
int | update_line (unsigned const tag, unsigned const idx, unsigned const offset, unsigned const way, unsigned const len, unsigned char *const data, sc_core::sc_time *delay, unsigned *debug, bool &cacheable, bool is_dbg) |
More... | |
int | allocate_line (unsigned const tag, unsigned const idx, unsigned const offset, unsigned const len, unsigned char *const data, sc_core::sc_time *delay, unsigned *debug, bool &cacheable, bool is_dbg) |
More... | |
Protected Attributes | |
Data | |
Constructors and Destructors | |
mmu_cache_if * | m_mmu_cache |
Pointer to the class with the amba interface. More... | |
mem_if * | m_tlb_adaptor |
Pointer to the class with the mmu interface. More... | |
unsigned int | CACHE_CONFIG_REG |
std::vector< t_cache_line > * | cache_mem |
The actual cache memory. More... | |
unsigned int | m_burst_en |
Indicates whether the cache can be put in burst mode or not. More... | |
bool | m_new_linefetch_en |
unsigned int | m_pseudo_rand |
Pseudo-random pointer. More... | |
Parameters | |
Data | |
unsigned int | m_sets |
Number of cache ways (000: direct mapped, 001: 2x, 010: 3x, 011: 4x) More... | |
unsigned int | m_setsize |
Size of cache way in kB = 2^m_waysize. More... | |
unsigned int | m_setlock |
Cache line locking. More... | |
unsigned int | m_linesize |
Size of cache line in words = 2^m_linesize. More... | |
unsigned int | m_wordsperline |
Number of words per cache line. More... | |
unsigned int | m_bytesperline |
Number of bytes per cache line. More... | |
unsigned int | m_offset_bits |
Number of bits for addressing the line offset. More... | |
unsigned int | m_number_of_vectors |
Number of lines in the cache. More... | |
unsigned int | m_idx_bits |
Address bits used for index. More... | |
unsigned int | m_tag_bits |
Address bits used for tag. More... | |
unsigned int | m_repl |
Replacement strategy. More... | |
unsigned int | m_mmu_en |
MMU enabled. More... | |
int | m_max_lru |
LRU counter maximum. More... | |
unsigned int | m_lram |
Local ram present. More... | |
unsigned int | m_lramstart |
Start address of localram (8 MSBs) More... | |
unsigned int | m_lramsize |
Size of localram. More... | |
Statistics | |
Parameters | |
gs::cnf::cnf_api * | m_api |
GreenControl API container. More... | |
gs::gs_param_array | m_performance_counters |
Open a namespace for performance counting in the greencontrol realm. More... | |
gs::gs_param< unsigned long long * > | rhits |
Counter for read hits. More... | |
sr_param< uint64_t > | rmisses |
Counter for read misses. More... | |
gs::gs_param< unsigned long long * > | whits |
Counter for write hits. More... | |
sr_param< uint64_t > | wmisses |
Counter for write misses. More... | |
sr_param< uint64_t > | bypassops |
Counter for bypass operations. More... | |
bool | m_pow_mon |
Enable power monitoring. More... | |
Timing and Power Modeling | |
Statistics | |
sr_param< uint64_t > | dyn_tag_reads |
Number of tag ram reads (monitor read & reset) More... | |
sr_param< uint64_t > | dyn_tag_writes |
Number of tag ram writes (monitor read & reset) More... | |
sr_param< uint64_t > | dyn_data_reads |
Number of data ram reads (monitor read & reset) More... | |
sr_param< uint64_t > | dyn_data_writes |
Number of data ram writes (monitor read & reset) More... | |
sc_core::sc_time | m_hit_read_response_delay |
Timing parameters. More... | |
sc_core::sc_time | m_miss_read_response_delay |
sc_core::sc_time | m_write_response_delay |
sc_core::sc_time | clockcycle |
Clock cycle time. More... | |
Constructors and Destructors | |
Diagnostic Methods | |
void | end_of_simulation () |
More... | |
vectorcache (ModuleName name, mmu_cache_if *_mmu_cache, mem_if *_tlb_adaptor, unsigned int mmu_en, unsigned int burst_en, bool new_linefetch_en, unsigned int sets, unsigned int setsize, unsigned int setlock, unsigned int linesize, unsigned int repl, unsigned int lram, unsigned int lramstart, unsigned int lramsize, bool pow_mon) | |
Constructor of data cache. More... | |
virtual | ~vectorcache () |
More... | |
Additional Inherited Members | |
Public Types inherited from cache_if | |
enum | t_cache_type { icache, dcache, nocache } |
Data type describing type of cache implementing this interface. More... | |
virtual cache model, contain common functionality of instruction and data cache
|
pure virtual |
Returns the mode bits of the cache.
Implements cache_if.
Implemented in ivectorcache, and dvectorcache.
Referenced by mem_read(), mem_write(), and snoop_invalidate().
|
inlineprotected |
References m_idx_bits, and m_offset_bits.
|
pure virtual |
Returns type of cache implementing this interface.
Implements cache_if.
Implemented in ivectorcache, and dvectorcache.
|
inlineprotected |
References m_offset_bits, and m_tag_bits.
Referenced by mem_read(), mem_write(), read_cache_entry(), read_cache_tag(), snoop_invalidate(), write_cache_entry(), and write_cache_tag().
|
inlineprotected |
References m_idx_bits, and m_tag_bits.
Referenced by mem_read(), mem_write(), and snoop_invalidate().
|
inlineprotected |
Address parsing one-liners.
References m_idx_bits, and m_offset_bits.
Referenced by mem_read(), mem_write(), read_cache_entry(), read_cache_tag(), snoop_invalidate(), write_cache_entry(), and write_cache_tag().
|
inlineprotected |
Reads a cache line from a given cache way. Returns an iterator to found line (more useful than pointer for looping through ways of a given index). Returns null for incorrect parameters.
References cache_mem, and m_sets.
Referenced by allocate_line(), dbg_out(), locate_line(), lrr_update(), lru_update(), mem_read(), read_cache_entry(), read_cache_tag(), replacement_selector(), snoop_invalidate(), update_line(), write_cache_entry(), and write_cache_tag().
Counter for bypass operations.
Referenced by end_of_simulation(), mem_read(), mem_write(), and vectorcache().
|
protected |
Cache configuration register (ASI 0x2): [3] MMU present - This bit is set to '1' if an MMU is present [11:4] Local RAM start address - The 8 MSBs of the local ram start address [15:12] Local RAM size (LRSZ) - Size in Kbytes of the local scratch pad ram (local RAM size = 2^LRSZ) [18:16] Line size (LSIZE) - The size (words) of each cache line (line size = 2^LSIZE) [19] Local RAM (LR) - Set if local scratch pad ram is implemented. [23:20] Way size (WSIZE) - Size in Kbytes of each cache way. (way size = 2^WSIZE) [26:24] Cache associativity (WAYS) - Number of ways in the cache (000 - direct mapped, 001 - 2-way associative, 010 - 3-way associative, 011 - 4-way associative) [27] Cache snooping (SN) - Set if snooping is implemented [29-28] Cache replacement policiy (REPL) (00 - no repl. (direct mapped), 01 - LRU, 10 - LRR, 11 - RANDOM) [31] Cache locking (CL) - Set if cache locking is implemented
Referenced by read_config_reg(), and vectorcache().
|
protected |
The actual cache memory.
Referenced by flush(), lookup_line(), and vectorcache().
|
protected |
Clock cycle time.
Referenced by clkcng(), locate_line(), mem_read(), mem_write(), dvectorcache::power_model(), ivectorcache::power_model(), read_cache_entry(), read_cache_tag(), read_config_reg(), update_line(), write_cache_entry(), and write_cache_tag().
Number of data ram reads (monitor read & reset)
Referenced by mem_read(), dvectorcache::swi_power_cb(), and ivectorcache::swi_power_cb().
Number of data ram writes (monitor read & reset)
Referenced by dvectorcache::swi_power_cb(), ivectorcache::swi_power_cb(), and update_line().
Number of tag ram reads (monitor read & reset)
Referenced by locate_line(), dvectorcache::swi_power_cb(), and ivectorcache::swi_power_cb().
Number of tag ram writes (monitor read & reset)
Referenced by dvectorcache::swi_power_cb(), ivectorcache::swi_power_cb(), and update_line().
|
protected |
GreenControl API container.
Referenced by vectorcache().
|
protected |
Indicates whether the cache can be put in burst mode or not.
Referenced by mem_read().
|
protected |
Number of bytes per cache line.
Referenced by mem_read(), offset2valid(), and vectorcache().
|
protected |
Timing parameters.
|
protected |
Address bits used for index.
Referenced by get_address(), get_offset(), get_tag(), and vectorcache().
|
protected |
Size of cache line in words = 2^m_linesize.
Referenced by mem_read(), and vectorcache().
|
protected |
Local ram present.
Referenced by vectorcache().
|
protected |
Size of localram.
Referenced by vectorcache().
|
protected |
Start address of localram (8 MSBs)
Referenced by vectorcache().
|
protected |
LRU counter maximum.
Referenced by lru_update(), replacement_selector(), and vectorcache().
|
protected |
|
protected |
Pointer to the class with the amba interface.
Referenced by dvectorcache::check_mode(), ivectorcache::check_mode(), and mem_read().
|
protected |
MMU enabled.
Referenced by vectorcache().
|
protected |
Enables linefetch mode for "newer" as used in "newer" versions of dcache in grlib
Referenced by allocate_line(), locate_line(), mem_read(), snoop_invalidate(), and update_line().
|
protected |
Number of lines in the cache.
Referenced by dvectorcache::power_model(), ivectorcache::power_model(), and vectorcache().
|
protected |
Number of bits for addressing the line offset.
Referenced by get_address(), get_idx(), get_tag(), read_cache_entry(), vectorcache(), and write_cache_entry().
|
protected |
Open a namespace for performance counting in the greencontrol realm.
|
protected |
Enable power monitoring.
Referenced by locate_line(), mem_read(), dvectorcache::start_of_simulation(), ivectorcache::start_of_simulation(), and update_line().
|
protected |
Pseudo-random pointer.
Referenced by replacement_selector().
|
protected |
Replacement strategy.
Referenced by allocate_line(), mem_read(), update_line(), and vectorcache().
|
protected |
Cache line locking.
Referenced by vectorcache(), and write_cache_tag().
|
protected |
Number of cache ways (000: direct mapped, 001: 2x, 010: 3x, 011: 4x)
Referenced by allocate_line(), dbg_out(), end_of_simulation(), locate_line(), lookup_line(), lru_update(), mem_read(), dvectorcache::power_model(), ivectorcache::power_model(), replacement_selector(), snoop_invalidate(), vectorcache(), and write_cache_tag().
|
protected |
Size of cache way in kB = 2^m_waysize.
Referenced by dvectorcache::power_model(), ivectorcache::power_model(), and vectorcache().
|
protected |
Address bits used for tag.
Referenced by get_idx(), get_offset(), and vectorcache().
|
protected |
Pointer to the class with the mmu interface.
Referenced by mem_read(), and mem_write().
|
protected |
Number of words per cache line.
Referenced by dbg_out().
|
protected |
|
protected |
Counter for read hits.
Referenced by end_of_simulation(), mem_read(), and vectorcache().
Counter for read misses.
Referenced by end_of_simulation(), mem_read(), and vectorcache().
|
protected |
Counter for write hits.
Referenced by end_of_simulation(), mem_write(), and vectorcache().
Counter for write misses.
Referenced by end_of_simulation(), mem_write(), and vectorcache().