Data cache implementation for TrapGen LEON3 simulator. More...

#include <dvectorcache.h>

Inheritance diagram for dvectorcache:

Collaboration diagram for dvectorcache:

Public Member Functions
	GC_HAS_CALLBACKS ()

unsigned int	check_mode ()
	Implement ccr check. More...

t_cache_type	get_cache_type ()
	Implement cache type function. More...

void	start_of_simulation ()
	Automatically called at start of simulation. More...

void	power_model ()
	Calculate power/energy values from normalized input data. More...

gs::cnf::callback_return_type	sta_power_cb (gs::gs_param_base &changed_param, gs::cnf::callback_type reason)
	Static power callback. More...

gs::cnf::callback_return_type	int_power_cb (gs::gs_param_base &changed_param, gs::cnf::callback_type reason)
	Dynamic/Internal power callback. More...

gs::cnf::callback_return_type	swi_power_cb (gs::gs_param_base &changed_param, gs::cnf::callback_type reason)
	Dynamic/Switching power callback. More...

	dvectorcache (ModuleName name, mmu_cache_if _mmu_cache, mem_if _tlb_adaptor, unsigned int mmu_en, unsigned int sets, unsigned int setsize, unsigned int setlock, unsigned int linesize, unsigned int repl, unsigned int lram, unsigned int lramstart, unsigned int lramsize, bool pow_mon)
	Constructor of data cache. More...

	~dvectorcache ()

Public Member Functions inherited from vectorcache
virtual bool	mem_read (unsigned int address, unsigned int asi, unsigned char data, unsigned int len, sc_core::sc_time t, unsigned int *debug, bool is_dbg, bool &cacheable, bool is_lock)
	Read from cache. More...

virtual void	mem_write (unsigned int address, unsigned int asi, unsigned char data, unsigned int len, sc_core::sc_time t, unsigned int *debug, bool is_dbg, bool &cacheable, bool is_lock)
	Write through cache. More...

virtual unsigned int	read_config_reg (sc_core::sc_time *t)
	Read cache configuration register (ASI 0x2) More...

virtual void	read_cache_tag (unsigned int address, unsigned int data, sc_core::sc_time t)
	Read data cache tags (ASI 0xe) More...

virtual void	write_cache_tag (unsigned int address, unsigned int data, sc_core::sc_time t)
	Write data cache tags (ASI 0xe) More...

virtual void	read_cache_entry (unsigned int address, unsigned int data, sc_core::sc_time t)
	Read data cache entries/data (ASI 0xf) More...

virtual void	write_cache_entry (unsigned int address, unsigned int data, sc_core::sc_time t)
	Write data cache entries/data (ASI 0xf) More...

virtual void	flush (sc_core::sc_time t, unsigned int debug, bool is_dbg)
	Flush cache. More...

virtual void	snoop_invalidate (const t_snoop &snoop, const sc_core::sc_time &delay)
	Snooping function (invalidates cache line(s)) More...

virtual void	dbg_out (unsigned int line)
	Display of cache lines for debug. More...

void	clkcng (sc_core::sc_time &clk)
	Helper functions for definition of clock cycle. More...

void	end_of_simulation ()
	More...

Public Member Functions inherited from cache_if
virtual	~cache_if ()

Public Member Functions inherited from mem_if
virtual	~mem_if ()

Public Attributes
sr_param< double >	sta_power_norm
	Normalized static power input for logic. More...

sr_param< double >	int_power_norm
	Normalized internal power input for logic (activation independent) More...

sr_param< double >	sta_dtag_power_norm
	Normalized static power input for dtag ram (dp) More...

sr_param< double >	sta_ddata_power_norm
	Normalized static power input for ddata ram (sp) More...

sr_param< double >	int_dtag_power_norm
	Normalized internal power input for dtag ram (dp) More...

sr_param< double >	int_ddata_power_norm
	Normalized internal power input for ddata ram (sp) More...

sr_param< double >	dyn_dtag_read_energy_norm
	Normalized read access energy for dtag ram (dp) More...

sr_param< double >	dyn_dtag_write_energy_norm
	Normalized write access energy for dtag ram (dp) More...

sr_param< double >	dyn_ddata_read_energy_norm
	Normalized read access energy for ddata ram (sp) More...

sr_param< double >	dyn_ddata_write_energy_norm
	Normalized write access energy for ddata ram (sp) More...

gs::gs_param_array	power
	Parameter array for power output (dcache controller) More...

sr_param< double >	sta_power
	Static power of module. More...

sr_param< double >	int_power
	Internal dynamic power (activation independent) More...

sr_param< double >	swi_power
	Switching power. More...

sr_param< sc_core::sc_time >	power_frame_starting_time
	Power frame starting time. More...

gs::gs_param_array	dtag
	Parameter array for power output of dtag ram. More...

sr_param< double >	dyn_tag_read_energy
	Dynamic energy per dtag read access. More...

sr_param< double >	dyn_tag_write_energy
	Dynamic energy per dtag write access. More...

gs::gs_param_array	ddata
	Parameter array for power output of ddata ram. More...

sr_param< double >	dyn_data_read_energy
	Dynamic energy per ddata read access. More...

sr_param< double >	dyn_data_write_energy
	Dynamic energy per ddata write access. More...

Additional Inherited Members
Public Types inherited from cache_if
enum	t_cache_type { icache, dcache, nocache }
	Data type describing type of cache implementing this interface. More...

Protected Member Functions inherited from vectorcache
unsigned	get_tag (unsigned address)
	Address parsing one-liners. More...

unsigned	get_idx (unsigned address)

unsigned	get_offset (unsigned address)

unsigned	get_address (unsigned tag, unsigned idx, unsigned offset)

unsigned int	offset2valid (unsigned int offset, unsigned int len=4)
	Transforms a cache-line offset into a valid mask. More...

unsigned int	replacement_selector (unsigned int idx, unsigned int mode)
	Returns number of the way to be refilled - depending on replacement strategy. More...

void	lru_update (unsigned int idx, unsigned int set_select)
	Updates the lru counters for every cache hit. More...

void	lrr_update (unsigned int idx, unsigned int set_select)
	Updates the lrr bits for every line replacement. More...

std::vector< t_cache_line > ::iterator	lookup_line (unsigned idx, unsigned way)

int	locate_line (unsigned const tag, unsigned const idx, unsigned const offset, unsigned const len, sc_core::sc_time *delay)
	More...

int	update_line (unsigned const tag, unsigned const idx, unsigned const offset, unsigned const way, unsigned const len, unsigned char const data, sc_core::sc_time delay, unsigned *debug, bool &cacheable, bool is_dbg)
	More...

int	allocate_line (unsigned const tag, unsigned const idx, unsigned const offset, unsigned const len, unsigned char const data, sc_core::sc_time delay, unsigned *debug, bool &cacheable, bool is_dbg)
	More...

	vectorcache (ModuleName name, mmu_cache_if _mmu_cache, mem_if _tlb_adaptor, unsigned int mmu_en, unsigned int burst_en, bool new_linefetch_en, unsigned int sets, unsigned int setsize, unsigned int setlock, unsigned int linesize, unsigned int repl, unsigned int lram, unsigned int lramstart, unsigned int lramsize, bool pow_mon)
	Constructor of data cache. More...

virtual	~vectorcache ()
	Enables power monitoring More...

Protected Attributes inherited from vectorcache
mmu_cache_if *	m_mmu_cache
	Pointer to the class with the amba interface. More...

mem_if *	m_tlb_adaptor
	Pointer to the class with the mmu interface. More...

unsigned int	CACHE_CONFIG_REG

std::vector< t_cache_line > *	cache_mem
	The actual cache memory. More...

unsigned int	m_burst_en
	Indicates whether the cache can be put in burst mode or not. More...

bool	m_new_linefetch_en

unsigned int	m_pseudo_rand
	Pseudo-random pointer. More...

unsigned int	m_sets
	Number of cache ways (000: direct mapped, 001: 2x, 010: 3x, 011: 4x) More...

unsigned int	m_setsize
	Size of cache way in kB = 2^m_waysize. More...

unsigned int	m_setlock
	Cache line locking. More...

unsigned int	m_linesize
	Size of cache line in words = 2^m_linesize. More...

unsigned int	m_wordsperline
	Number of words per cache line. More...

unsigned int	m_bytesperline
	Number of bytes per cache line. More...

unsigned int	m_offset_bits
	Number of bits for addressing the line offset. More...

unsigned int	m_number_of_vectors
	Number of lines in the cache. More...

unsigned int	m_idx_bits
	Address bits used for index. More...

unsigned int	m_tag_bits
	Address bits used for tag. More...

unsigned int	m_repl
	Replacement strategy. More...

unsigned int	m_mmu_en
	MMU enabled. More...

int	m_max_lru
	LRU counter maximum. More...

unsigned int	m_lram
	Local ram present. More...

unsigned int	m_lramstart
	Start address of localram (8 MSBs) More...

unsigned int	m_lramsize
	Size of localram. More...

gs::cnf::cnf_api *	m_api
	GreenControl API container. More...

gs::gs_param_array	m_performance_counters
	Open a namespace for performance counting in the greencontrol realm. More...

gs::gs_param< unsigned long long * >	rhits
	Counter for read hits. More...

sr_param< uint64_t >	rmisses
	Counter for read misses. More...

gs::gs_param< unsigned long long * >	whits
	Counter for write hits. More...

sr_param< uint64_t >	wmisses
	Counter for write misses. More...

sr_param< uint64_t >	bypassops
	Counter for bypass operations. More...

bool	m_pow_mon
	Enable power monitoring. More...

sr_param< uint64_t >	dyn_tag_reads
	Number of tag ram reads (monitor read & reset) More...

sr_param< uint64_t >	dyn_tag_writes
	Number of tag ram writes (monitor read & reset) More...

sr_param< uint64_t >	dyn_data_reads
	Number of data ram reads (monitor read & reset) More...

sr_param< uint64_t >	dyn_data_writes
	Number of data ram writes (monitor read & reset) More...

sc_core::sc_time	m_hit_read_response_delay
	Timing parameters. More...

sc_core::sc_time	m_miss_read_response_delay

sc_core::sc_time	m_write_response_delay

sc_core::sc_time	clockcycle
	Clock cycle time. More...

Detailed Description

Data cache implementation for TrapGen LEON3 simulator.

Constructor & Destructor Documentation

dvectorcache::dvectorcache	(	ModuleName	name,
		mmu_cache_if *	_mmu_cache,
		mem_if *	_tlb_adaptor,
		unsigned int	mmu_en,
		unsigned int	sets,
		unsigned int	setsize,
		unsigned int	setlock,
		unsigned int	linesize,
		unsigned int	repl,
		unsigned int	lram,
		unsigned int	lramstart,
		unsigned int	lramsize,
		bool	pow_mon
	)

inline

Constructor of data cache.

Parameters

name	SystemC module name
mmu_cache	Pointer to top-level class of cache subsystem (mmu_cache) for access to AHB bus interface
tlb_adaptor	Pointer to memory management unit
hit_read_response_delay	Delay for a cache read hit
miss_read_response_delay	Delay for a cache read miss
write_response_delay	Delay for a cache write access (hit/miss)
sets	Number of cache sets
setsize	Size of a cache set (in kbytes)
setlock	Enable cache line locking
linesize	Size of a cache line (in bytes)
repl	Cache replacement strategy
lram	Local RAM configured
lramstart	The 8 MSBs of the local ram start address (16MB segment)
lramsize	Size of local ram (size in kbyte = 2^lramsize)

References int_power, usi.cci.callback::pre_read, sta_power, and swi_power.

dvectorcache::~dvectorcache ( )

inline

Member Function Documentation

dvectorcache::GC_HAS_CALLBACKS ( )

Member Data Documentation

gs::gs_param_array dvectorcache::ddata

Parameter array for power output of ddata ram.

gs::gs_param_array dvectorcache::dtag

Parameter array for power output of dtag ram.

sr_param<double> dvectorcache::dyn_data_read_energy

Dynamic energy per ddata read access.

Referenced by power_model(), and swi_power_cb().

sr_param<double> dvectorcache::dyn_data_write_energy

Dynamic energy per ddata write access.

Referenced by power_model(), and swi_power_cb().

sr_param<double> dvectorcache::dyn_ddata_read_energy_norm

Normalized read access energy for ddata ram (sp)

Referenced by power_model().

sr_param<double> dvectorcache::dyn_ddata_write_energy_norm

Normalized write access energy for ddata ram (sp)

Referenced by power_model().

sr_param<double> dvectorcache::dyn_dtag_read_energy_norm

Normalized read access energy for dtag ram (dp)

Referenced by power_model().

sr_param<double> dvectorcache::dyn_dtag_write_energy_norm

Normalized write access energy for dtag ram (dp)

Referenced by power_model().

sr_param<double> dvectorcache::dyn_tag_read_energy

Dynamic energy per dtag read access.

Referenced by power_model(), and swi_power_cb().

sr_param<double> dvectorcache::dyn_tag_write_energy

Dynamic energy per dtag write access.

Referenced by power_model(), and swi_power_cb().

sr_param<double> dvectorcache::int_ddata_power_norm

Normalized internal power input for ddata ram (sp)

Referenced by power_model().

sr_param<double> dvectorcache::int_dtag_power_norm

Normalized internal power input for dtag ram (dp)

Referenced by power_model().

sr_param<double> dvectorcache::int_power

Internal dynamic power (activation independent)

Referenced by dvectorcache(), and power_model().

sr_param<double> dvectorcache::int_power_norm

Normalized internal power input for logic (activation independent)

Referenced by power_model().

gs::gs_param_array dvectorcache::power

Parameter array for power output (dcache controller)

sr_param<sc_core::sc_time> dvectorcache::power_frame_starting_time

Power frame starting time.

Referenced by swi_power_cb().

sr_param<double> dvectorcache::sta_ddata_power_norm

Normalized static power input for ddata ram (sp)

Referenced by power_model().

sr_param<double> dvectorcache::sta_dtag_power_norm

Normalized static power input for dtag ram (dp)

Referenced by power_model().

sr_param<double> dvectorcache::sta_power

Static power of module.

Referenced by dvectorcache(), and power_model().

sr_param<double> dvectorcache::sta_power_norm

Normalized static power input for logic.

Power Modeling Parameters

Referenced by power_model().

sr_param<double> dvectorcache::swi_power

Switching power.

Referenced by dvectorcache(), and swi_power_cb().

The documentation for this class was generated from the following files:

gaisler/leon3/mmucache/dvectorcache.h
gaisler/leon3/mmucache/dvectorcache.cpp

Public Member Functions

Public Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation

Member Data Documentation